US Patent Application 17748632. Isolation Structure And A Self-Aligned Capping Layer Formed Thereon simplified abstract
Contents
Isolation Structure And A Self-Aligned Capping Layer Formed Thereon
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chen-Ming Lee of Taoyuan County (TW)
Fu-Kai Yang of Hsinchu City (TW)
Isolation Structure And A Self-Aligned Capping Layer Formed Thereon - A simplified explanation of the abstract
This abstract first appeared for US patent application 17748632 titled 'Isolation Structure And A Self-Aligned Capping Layer Formed Thereon
Simplified Explanation
- The patent application describes a method for creating semiconductor structures. - The method involves using a workpiece with a semiconductor fin protruding from a substrate, along with placeholder gates and a source/drain feature. - The first step is to remove a portion of the first placeholder gate and the substrate underneath to create an isolation trench. - A dielectric feature is then formed in the isolation trench. - The second placeholder gate is replaced with a metal gate stack. - The dielectric feature is selectively recessed. - A first capping layer is formed over the metal gate stack and a second capping layer is formed over the recessed dielectric feature. - Finally, a source/drain contact is formed and electrically connected to the source/drain feature.
Original Abstract Submitted
Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.
