US Patent Application 17746381. INTEGRATED CIRCUITS HAVING SIGNAL LINES FORMED WITH DOUBLE PATTERNING simplified abstract
Contents
INTEGRATED CIRCUITS HAVING SIGNAL LINES FORMED WITH DOUBLE PATTERNING
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chung-Chieh Yang of Hsinchu (TW)
Yung-Chow Peng of Hsinchu (TW)
INTEGRATED CIRCUITS HAVING SIGNAL LINES FORMED WITH DOUBLE PATTERNING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17746381 titled 'INTEGRATED CIRCUITS HAVING SIGNAL LINES FORMED WITH DOUBLE PATTERNING
Simplified Explanation
The patent application describes an integrated circuit that includes metal conducting lines in a metal layer over an insulation layer on a substrate.
- Metal conducting lines are arranged in an array.
- A first metal segment lineup is present between two metal conducting lines in the array.
- An electric circuit is connected to the first and second metal conducting lines.
- The first and second metal conducting lines have equal lengths.
Original Abstract Submitted
An integrated circuit includes an array of metal conducting lines in a metal layer overlying an insulation layer supported by a substrate, a first metal segment lineup having multiple metal segments in the metal layer between a first metal conducting line and a second metal conducting line in the array of metal conducting lines, and an electric circuit having a first input and a second input. The first input is connected to the first metal conducting line and the second input is connected to the second metal conducting line, and a first length of the first metal conducting line is equal to a second length of the second metal conducting line.
