US Patent Application 17659214. INTEGRATED CIRCUITS (ICS) EMPLOYING MULTI-PATTERN METALLIZATION TO OPTIMIZE METAL INTERCONNECT SPACING FOR IMPROVED PERFORMANCE AND RELATED FABRICATION METHODS simplified abstract

INTEGRATED CIRCUITS (ICS) EMPLOYING MULTI-PATTERN METALLIZATION TO OPTIMIZE METAL INTERCONNECT SPACING FOR IMPROVED PERFORMANCE AND RELATED FABRICATION METHODS

Organization Name

QUALCOMM Incorporated

Inventor(s)

Bed Raj Kandel of San Diego CA (US)

Katherine Zhang of San Diego CA (US)

Thomas Hua-Min Williams of Irvine CA (US)

INTEGRATED CIRCUITS (ICS) EMPLOYING MULTI-PATTERN METALLIZATION TO OPTIMIZE METAL INTERCONNECT SPACING FOR IMPROVED PERFORMANCE AND RELATED FABRICATION METHODS - A simplified explanation of the abstract

• This abstract for appeared for US patent application number 17659214 Titled 'INTEGRATED CIRCUITS (ICS) EMPLOYING MULTI-PATTERN METALLIZATION TO OPTIMIZE METAL INTERCONNECT SPACING FOR IMPROVED PERFORMANCE AND RELATED FABRICATION METHODS'

Simplified Explanation

This abstract describes a new design for integrated circuits (ICs) that includes transistors formed in diffusion regions. The transistors have a source and a drain that extend in one direction, with a gate in between. To reduce resistance in the connections between the transistors and the metal lines, one of the metal lines (either the source or the drain) is extended further in that direction. This provides more space for the interconnection via, which reduces resistance without increasing capacitance between the metal lines. By increasing the landing area for the via, the resistance to the source and/or drain is reduced. This design also allows the via landing area to be shifted in the same direction, further reducing capacitance.

Original Abstract Submitted

An integrated circuit (IC) includes transistors formed in diffusion regions. In each transistor, a source and a drain extend in a first direction, and a gate is disposed on the diffusion region between the source and the drain. To reduce connection resistance through at least one of a source metal line and a drain metal line connected to the source and the drain of a transistor, one of the source metal line and the drain metal line extends farther than the other in the first direction to provide additional via landing area to support an interconnection via having reduced resistance without increasing side-to-side capacitance between the source and drain metal lines. Increasing the via landing area reduces connection resistance to the source and/or drain. Providing an extended source metal line and/or drain metal line allows a via landing area to be shifted in the first direction to reduce via capacitance.