Taiwan semiconductor manufacturing company, ltd. (20240112959). Multi-Gate Device And Related Methods simplified abstract

Multi-Gate Device And Related Methods

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Kuan-Ting Pan of Taipei City (TW)

Zhi-Chang Lin of Hsinchu County (TW)

Yi-Ruei Jhan of Keelung City (TW)

Chi-Hao Wang of Hsinchu County (TW)

Huan-Chieh Su of Changhua County (TW)

Shi Ning Ju of Hsinchu City (TW)

Kuo-Cheng Chiang of Hsinchu County (TW)

Multi-Gate Device And Related Methods - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240112959 titled 'Multi-Gate Device And Related Methods

Simplified Explanation

The method described in the abstract involves fabricating a device by forming a dummy gate over a plurality of fins, removing portions of the dummy gate to create trenches, filling the trenches with dielectric material and metal layer, and etching-back the metal layer to achieve specific dimensions.

• Formation of dummy gate over fins
• Removal of portions of dummy gate to create trenches
• Filling trenches with dielectric material and metal layer
• Etching-back of metal layer to achieve desired dimensions

Potential Applications

The technology described in this patent application could be applied in the manufacturing of advanced semiconductor devices, particularly in the fabrication of transistors with hybrid fin structures.

Problems Solved

This technology addresses the challenge of precise and controlled fabrication of semiconductor devices with complex fin structures, ensuring optimal performance and efficiency.

Benefits

The benefits of this technology include improved device performance, enhanced efficiency, and the ability to create advanced semiconductor devices with intricate fin structures.

Potential Commercial Applications

The potential commercial applications of this technology include the production of high-performance processors, memory chips, and other semiconductor devices for various electronic applications.

Possible Prior Art

One possible prior art related to this technology is the use of dummy gates in semiconductor fabrication processes to create precise structures and enhance device performance.

How does this technology compare to existing methods for fabricating semiconductor devices with hybrid fin structures?

This article does not provide a direct comparison between this technology and existing methods for fabricating semiconductor devices with hybrid fin structures.

What are the specific dimensions and materials used in the fabrication process described in the patent application?

The article does not specify the exact dimensions and materials used in the fabrication process described in the patent application.

Original Abstract Submitted

a method of fabricating a device includes forming a dummy gate over a plurality of fins. thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. the method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. the method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.