Taiwan semiconductor manufacturing company, ltd. (20240105629). SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract

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SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Chen-Hsuan Tsai of Taitung City (TW)

Chin-Chuan Chang of Hsinchu County (TW)

Szu-Wei Lu of Hsinchu City (TW)

Tsung-Fu Tsai of Changhua County (TW)

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240105629 titled 'SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The semiconductor package described in the patent application includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is positioned next to the first semiconductor die, with the semiconductor bridge connecting the two dies electrically. The integrated passive device is connected to the first semiconductor die, and the first redistribution layer is placed over the semiconductor bridge. The connective terminals are located on the opposite side of the first redistribution layer with respect to the semiconductor bridge, with the first redistribution layer acting as a barrier between the integrated passive device and the connective terminals.

  • The semiconductor package includes two semiconductor dies, a bridge, an integrated passive device, a redistribution layer, and connective terminals.
  • The bridge electrically connects the two semiconductor dies, while the integrated passive device is connected to the first semiconductor die.
  • The connective terminals are placed on the first redistribution layer, which separates them from the integrated passive device.

Potential Applications

The technology described in this patent application could be applied in various electronic devices requiring compact and efficient semiconductor packaging, such as smartphones, tablets, and IoT devices.

Problems Solved

This innovation solves the problem of efficiently connecting multiple semiconductor dies within a compact package while ensuring proper electrical connections and thermal management.

Benefits

The benefits of this technology include improved performance, reduced size and weight of electronic devices, enhanced thermal management, and potentially lower manufacturing costs.

Potential Commercial Applications

The semiconductor package described in this patent application could find commercial applications in the consumer electronics industry, particularly in the development of smaller and more powerful devices.

Possible Prior Art

One possible prior art for this technology could be the use of stacked die packaging in semiconductor devices to achieve compact designs and improved performance.

Unanswered Questions

How does this technology compare to traditional semiconductor packaging methods?

The article does not provide a direct comparison between this technology and traditional semiconductor packaging methods in terms of performance, size, cost, or other factors.

What are the specific technical specifications of the integrated passive device mentioned in the patent application?

The article does not delve into the technical specifications or capabilities of the integrated passive device used in the semiconductor package.


Original Abstract Submitted

a semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. the second semiconductor die is disposed beside the first semiconductor die. the semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. the integrated passive device is electrically connected to the first semiconductor die. the first redistribution layer is disposed over the semiconductor bridge. the connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. the first redistribution layer is interposed between the integrated passive device and the connective terminals.