Taiwan semiconductor manufacturing co., ltd. (20240099151). SUB 60NM ETCHLESS MRAM DEVICES BY ION BEAM ETCHING FABRICATED T-SHAPED BOTTOM ELECTRODE simplified abstract

SUB 60NM ETCHLESS MRAM DEVICES BY ION BEAM ETCHING FABRICATED T-SHAPED BOTTOM ELECTRODE

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Yi Yang of Fremont CA (US)

Dongna Shen of San Jose CA (US)

Yu-Jen Wang of San Jose CA (US)

SUB 60NM ETCHLESS MRAM DEVICES BY ION BEAM ETCHING FABRICATED T-SHAPED BOTTOM ELECTRODE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240099151 titled 'SUB 60NM ETCHLESS MRAM DEVICES BY ION BEAM ETCHING FABRICATED T-SHAPED BOTTOM ELECTRODE

Simplified Explanation

The patent application describes a method for fabricating a sub-30 nm conductive via on a bottom electrode, followed by the deposition of a second conductive layer to form a T-shaped bottom electrode for magnetic tunnel junction (MTJ) stacks.

• Patterning and trimming of a first conductive layer to create a sub-30 nm conductive via on a bottom electrode
• Encapsulating the conductive via with a dielectric layer and planarizing to expose the top surface
• Depositing a second conductive layer over the first dielectric layer and the conductive via
• Patterning the second conductive layer to form a sub-60 nm second conductive layer, creating a T-shaped bottom electrode
• Depositing MTJ stacks on the T-shaped second bottom electrode and the first bottom electrode
• Depositing a second dielectric layer over the MTJ stacks and planarizing to expose the top surface of the MTJ stack on the T-shaped second bottom electrode
• Connecting a top electrode to the MTJ stack on the T-shaped second bottom electrode plug

Potential Applications

This technology could be applied in the development of advanced memory devices, such as magnetic random-access memory (MRAM) and spin-transfer torque random-access memory (STT-RAM).

Problems Solved

This technology solves the challenge of fabricating sub-30 nm conductive vias and sub-60 nm second conductive layers for MTJ stacks, enabling the production of high-density and high-performance memory devices.

Benefits

The benefits of this technology include improved memory device performance, increased memory density, and enhanced reliability due to the precise fabrication of sub-30 nm conductive vias and sub-60 nm second conductive layers.

Potential Commercial Applications

• "Advanced Memory Device Fabrication Using Sub-30 nm Conductive Vias and Sub-60 nm Second Conductive Layers"

Possible Prior Art

One possible prior art for this technology could be the fabrication methods for sub-30 nm conductive vias and sub-60 nm conductive layers in semiconductor devices.

How does this technology compare to existing methods for fabricating memory devices?

This technology offers a more precise and efficient method for fabricating high-density memory devices, but further comparison studies with existing methods are needed to evaluate its advantages.

What are the potential challenges in scaling up this fabrication process for mass production?

Scaling up this fabrication process for mass production may face challenges related to cost, yield, and process stability. Further research and development are required to address these challenges.

Original Abstract Submitted

a first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. the conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. a second conductive layer is deposited over the first dielectric layer and the conductive via. the second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a t-shaped second bottom electrode. mtj stacks are deposited on the t-shaped second bottom electrode and on the first bottom electrode wherein the mtj stacks are discontinuous. a second dielectric layer is deposited over the mtj stacks and planarized to expose a top surface of the mtj stack on the t-shaped second bottom electrode. a top electrode contacts the mtj stack on the t-shaped second bottom electrode plug.