Taiwan semiconductor manufacturing co., ltd. (20240096998). HYBRID CONDUCTIVE STRUCTURES simplified abstract

HYBRID CONDUCTIVE STRUCTURES

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Shuen-Shin Liang of Hsinchu County (TW)

Chij-chien Chi of Hsinchu City (TW)

Yi-Ying Liu of Hsinchu City (TW)

Chia-Hung Chu of Hsinchu City (TW)

Hsu-Kai Chang of Hsinchu (TW)

Cheng-Wei Chang of Taipei (TW)

Chein-Shun Liao of New Taipei City (TW)

Keng-chu Lin of Ping-Tung (TW)

KAi-Ting Huang of Hsinchu (TW)

HYBRID CONDUCTIVE STRUCTURES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240096998 titled 'HYBRID CONDUCTIVE STRUCTURES

Simplified Explanation

The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

• Deposit first dielectric on substrate with gate and S/D structures
• Form opening in dielectric to expose S/D structures
• Deposit ruthenium metal on bottom and sidewall surfaces of opening
• Deposit cobalt metal to fill the opening
• Reflow cobalt metal and planarize to form S/D conductive structures

Potential Applications

This technology can be applied in semiconductor manufacturing processes, specifically in the fabrication of advanced integrated circuits.

Problems Solved

1. Improved conductivity and reliability of S/D structures in semiconductor devices. 2. Enhanced adhesion and barrier properties of metallization layers.

Benefits

1. Higher performance and efficiency of integrated circuits. 2. Increased durability and longevity of semiconductor devices. 3. Cost-effective manufacturing process.

Potential Commercial Applications

Optimizing metallization layers in semiconductor devices for improved performance and reliability.

Possible Prior Art

Prior art may include patents or publications related to the deposition and planarization of metal layers in semiconductor manufacturing processes.

Unanswered Questions

How does this method compare to existing techniques for forming metallization layers in semiconductor devices?

The article does not provide a direct comparison with existing techniques, making it unclear how this method stands out in terms of efficiency and effectiveness.

What are the specific parameters for depositing and planarizing the cobalt and ruthenium metals in this method?

The article lacks detailed information on the specific parameters and conditions required for the deposition and planarization processes, leaving room for further clarification on the operational aspects of the method.

Original Abstract Submitted

the present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. the method includes depositing a first dielectric on a substrate having a gate structure and source/drain (s/d) structures, forming an opening in the first dielectric to expose the s/d structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. the method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form s/d conductive structures with a top surface coplanar with a top surface of the first dielectric.