Taiwan semiconductor manufacturing co., ltd. (20240096880). WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES simplified abstract

WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Mao-Lin Huang of Hsinchu City (TW)

Chih-Hao Wang of Baoshan Township (TW)

Kuo-Cheng Chiang of Zhubei City (TW)

Jia-Ni Yu of New Taipei City (TW)

Lung-Kun Chu of New Taipei City (TW)

Chung-Wei Hsu of Hsinchu County (TW)

WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240096880 titled 'WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES

Simplified Explanation

The present disclosure relates to an integrated chip with multiple transistor devices and gate electrode layers wrapping around the channel structures.

• The integrated chip includes multiple channel structures for transporting charge carriers within different transistor devices.
• Each transistor device has a corresponding gate electrode layer that wraps around the channel structure.
• The gate electrode layers continuously extend to cover the gate electrode layers of adjacent transistor devices.

Potential Applications

This technology could be applied in:

• Integrated circuits
• Semiconductor devices
• Electronic components

Problems Solved

This technology helps in:

• Improving the efficiency of charge carrier transport
• Enhancing the performance of transistor devices
• Optimizing the layout of integrated chips

Benefits

The benefits of this technology include:

• Increased functionality of integrated chips
• Higher speed and reliability of semiconductor devices
• Enhanced overall performance of electronic components

Potential Commercial Applications

The potential commercial applications of this technology could be in:

• Consumer electronics
• Telecommunications
• Automotive industry

Possible Prior Art

One possible prior art could be the use of gate electrode layers in semiconductor devices to control the flow of charge carriers.

What materials are used in the fabrication of the integrated chip?

Materials such as silicon, metal layers, and insulating materials are commonly used in the fabrication of integrated chips.

How does the design of the gate electrode layers impact the performance of the transistor devices?

The design of the gate electrode layers can affect factors such as charge carrier mobility, threshold voltage, and overall efficiency of the transistor devices.

Original Abstract Submitted

in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. a second channel structure is configured to transport charge carriers within a second transistor device. a second gate electrode layer wraps around the second channel structure. the second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. a third channel structure is configured to transport charge carriers within a third transistor device. a third gate electrode layer wraps around the third channel structure. the third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.