Taiwan semiconductor manufacturing co., ltd. (20240096722). Fan-Out Stacked Package and Methods of Making the Same simplified abstract

Fan-Out Stacked Package and Methods of Making the Same

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Kuo-Chung Yee of Taoyuan City (TW)

Chia-Hui Lin of Shengang Township (TW)

Shih-Peng Tai of Xinpu Township (TW)

Fan-Out Stacked Package and Methods of Making the Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240096722 titled 'Fan-Out Stacked Package and Methods of Making the Same

Simplified Explanation

The abstract describes a package containing two devices with redistribution structures, encapsulants, and vias, all arranged in a specific configuration.

• The package includes a first device and a second device attached to a first redistribution structure.
• The second device has a second redistribution structure, a first die, encapsulants, vias, and a third redistribution structure with a second die.
• The package has a third encapsulant surrounding the devices and redistribution structures, with top surfaces of the encapsulants being level.

Potential Applications

This technology could be applied in the semiconductor industry for advanced packaging solutions, such as in mobile devices, IoT devices, and automotive electronics.

Problems Solved

This technology solves the problem of optimizing space and connectivity within a package, allowing for efficient integration of multiple devices without through substrate vias.

Benefits

The benefits of this technology include improved reliability, reduced signal interference, enhanced thermal performance, and overall cost-effectiveness in semiconductor packaging.

Potential Commercial Applications

"Advanced Semiconductor Packaging Solutions for Enhanced Device Integration"

Possible Prior Art

One possible prior art in semiconductor packaging is the use of through substrate vias for interconnecting multiple dies within a package. This new technology eliminates the need for such vias, offering a different approach to device integration.

How does this technology impact the overall size of the package and its integration into different electronic devices?

This article does not provide specific details on the size reduction or integration aspects of the package. Further research or testing may be needed to determine the exact impact on package size and integration flexibility.

What are the potential challenges in manufacturing and scaling up production using this technology?

The article does not address the manufacturing challenges or scalability issues that may arise with this technology. Additional studies or industry insights could shed light on the practical implications of implementing this packaging solution on a larger scale.

Original Abstract Submitted

in an embodiment, a package includes a first device and a second device attached to a first redistribution structure, wherein the second device includes a second redistribution structure, a first die disposed over the second redistribution structure, a first encapsulant extending along sidewalls of the first die, a first via extending through the first encapsulant, a third redistribution structure disposed over the first encapsulant and including a first metallization pattern connecting to the first via, a second die disposed over the third redistribution structure, and a second encapsulant extending along sidewalls of the second die, the first die and the second die being free of through substrate vias. the package also includes a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first device and the second device, wherein top surfaces of the second encapsulant and the third encapsulant are level with each other.