Taiwan Semiconductor manufacturing Co., Ltd. patent applications on April 18th, 2024
Patent Applications by Taiwan Semiconductor manufacturing Co., Ltd. on April 18th, 2024
Taiwan Semiconductor manufacturing Co., Ltd.: 38 patent applications
Taiwan Semiconductor manufacturing Co., Ltd. has applied for patents in the areas of H01L23/00 (13), H01L21/56 (8), H01L29/66 (7), H01L23/31 (7), H01L24/08 (7)
With keywords such as: layer, semiconductor, substrate, structure, die, dielectric, disposed, gate, bonding, and conductive in patent application abstracts.
Patent Applications by Taiwan Semiconductor manufacturing Co., Ltd.
Inventor(s): Yun-Chung Wu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jhao-Yi Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Hao Chun Yang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Wei Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hsiung Lu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B81C1/00, B81B7/00
Abstract: microelectromechanical devices and methods of manufacture are presented. embodiments include bonding a mask substrate to a first microelectromechanical system (mems) device. after the bonding has been performed, the mask substrate is patterned. a first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. the mask substrate is then removed.
Inventor(s): Hao Chun Yang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Da Cheng of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Wei Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Mirng-Ji Lii of Sinpu Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N21/95, G01N21/59
Abstract: a method includes directing light at a first side of a semiconductor structure; detecting a first light intensity at a second side of the semiconductor structure, wherein the first light intensity corresponds to the light that penetrated the semiconductor structure from the first side to the second side; and comparing the first light intensity to a second light intensity, wherein the second light intensity corresponds to an expected intensity of light.
Inventor(s): Chun-Chih HO of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Hsiang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu Chang of Yuansun Village (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/038, G03F7/20, H01L21/027
Abstract: a method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. the photoresist layer is selectively exposed to actinic radiation, the selectively exposed photoresist layer is developed to form a pattern in the photoresist layer. the photoresist composition includes a polymer including monomer units with photocleaving promoters, wherein the photocleaving promoters are one or more selected from the group consisting of living free radical polymerization chain transfer agents, electron withdrawing groups, bulky two dimensional (2-d) or three dimensional (3-d) organic groups, n-(acyloxy)phthalimides, and electron stimulated radical generators.
20240126174.LITHOGRAPHY_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Meng-Che Tu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Han Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sih-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/20, H01L21/027, H01L21/768
Abstract: a method includes the following steps. a photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. the photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.
Inventor(s): Ching Hsu of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Heng-Yi Lin of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Lin Chuang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/398, G06F30/392, G06F30/394
Abstract: a method includes: identifying a first design rule check (drc) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first drc violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.
Inventor(s): Hiroki NOGUCHI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ku-Feng LIN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C13/00
Abstract: a memory device is provided. the memory device includes several sense amplifiers and at least one reference cell. each of the sense amplifiers has a first terminal and a second terminal. the first terminals of the sense amplifiers are coupled to a memory cell block, and the second terminals of the sense amplifiers are coupled together to transmit a read current. the at least one reference cell transmits the read current to a ground terminal. the at least one reference cell has a decreased resistance value when a number n of the sense amplifiers increases.
Inventor(s): Qun DENG of Nanchang City (CN) for taiwan semiconductor manufacturing co., ltd., Guang YANG of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Qinhong ZHANG of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Zihao CAO of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/67, H01L21/677
Abstract: a method includes receiving, by a control module of a wafer transport system, an indication of wafer transporting; calculating, by the control module, a route for transporting a first wafer carrier according to the indication; moving, by a control unit of a wafer transport device of the wafer transport system, the wafer transport device to a first stocker storing the first wafer carrier along the route; performing, by the control unit, a safety monitoring process during a movement of the wafer transport device; stopping, by the control unit, the wafer transport device in front of the first stocker; and identifying, by an identification device of the wafer transport device, the first wafer carrier loaded on a rack of the wafer transport device.
Inventor(s): Hsiang-Wei Liu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Kuang Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/302, H01L21/48, H01L21/56, H01L21/762, H01L23/538
Abstract: a package structure and a manufacturing method thereof are disclosed. the structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. the connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. the redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.
20240128122.SEMICONDUCTOR PACKAGE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Wei-Chung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/48, H01L25/10
Abstract: semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. first barrier layer extends on backside surface. second barrier layer extends along sidewalls of through hole and on frontside surface. routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. first routing pattern extends over first barrier layer on backside surface and over routing via. first routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. second routing pattern extends over second barrier layer on frontside surface. second routing pattern directly contacts another end of routing via. semiconductor die is electrically connected to routing via by first routing pattern.
Inventor(s): Winnie Victoria Wei-Ning Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Ling Pai of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Pang-Yen Tsai of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L29/06, H01L29/423, H01L29/66
Abstract: a method of forming a semiconductor device includes providing a substrate having a recess, and growing an epitaxial feature in the recess. the method of growing the epitaxial feature includes: (a) growing a sub-layer of the epitaxial feature; (b) selectively etching the sub-layer of the epitaxial feature while providing a first uv radiation; and (c) repeating step (a) and step (b) alternately multiple times.
Inventor(s): Shu-Uei Jang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Huang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shiang-Bau Wang of Pingzchen City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Yuan Ku of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L21/033, H01L21/308, H01L21/762, H01L27/088, H01L29/66, H01L29/78
Abstract: a conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. an oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.
Inventor(s): Chia-Han Hsieh of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jin Hu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Hua-Wei Tseng of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsin-chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L21/78, H01L23/00
Abstract: provided are a package structure and a method of forming the same. the method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.
20240128147.SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Sey-Ping SUN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua YU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih Wei LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L23/00, H01L23/373, H10B80/00
Abstract: a semiconductor device is provided. the semiconductor includes a supporting silicon layer and a memory module. the memory module and the supporting silicon layer are bonded via a bonding structure. the bonding structure includes at least one bonding film whose thickness is less than 200 Å.
Inventor(s): Chang-Jung Hsueh of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao Lin of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Min Huang of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Kathy Yan of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L23/00, H10B80/00
Abstract: a method includes attaching a package component to a package substrate, the package component includes: an interposer disposed over the package substrate; a first die disposed along the interposer; and a second die disposed along the interposer, the second die being laterally adjacent the first die; attaching a first thermal interface material to the first die, the first thermal interface material being composed of a first material; attaching a second thermal interface material to the second die, the second thermal interface material being composed of a second material different from the first material; and attaching a lid assembly to the package substrate, the lid assembly being further attached to the first thermal interface material and the second thermal interface material.
Inventor(s): Cheng-Chieh HSIEH of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Kong SHENG of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Han SHEN of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jen LIEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L23/00, H01L23/31
Abstract: some implementations described herein include systems and techniques for fabricating a semiconductor die package that includes a cooling interface region formed in surface of an integrated circuit die. the cooling interface region, which includes a combination of channel regions and pillar structures, may be directly exposed to a fluid above and/or around the semiconductor die package.
Inventor(s): Chin-Chuan Chang of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/56, H01L21/768, H01L23/00, H01L23/498, H01L25/065, H01L25/10
Abstract: a method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. first connectors are formed over the set of through-vias on a first side of the substrate. the first side of the substrate is attached to a carrier. the substrate is thinned from the second side to expose the set of through-vias. second connectors are formed over the set of through-vias on the second side of the substrate. a device die is bonded to the second connectors. the substrate is singulated into multiple packages.
Inventor(s): Yu-Hung LIN of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Ming WANG of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Su-Chun YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Jih-Churng TWU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Peng TAI of Xinpu Township (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chung YEE of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L21/762, H01L23/29
Abstract: a method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. a conductive structure is formed in the first substrate. the method includes bonding the first substrate to a carrier. the method includes thinning down the first substrate. the method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. the method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. in addition, the method includes removing the carrier from the first substrate.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Han Lee of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Lee-Chung Lu of Taipei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/82, H01L23/00, H01L23/498, H01L25/065
Abstract: integrated circuit packages and methods of forming the same are provided. in an embodiment, a device includes: a power distribution interposer including: a first bonding layer; a first die connector in the first bonding layer; and a back-side interconnect structure including a power rail connected to the first die connector; and an integrated circuit die including: a second bonding layer directly bonded to the first bonding layer by dielectric-to-dielectric bonds; a second die connector in the second bonding layer, the second die connector directly bonded to the first die connector by metal-to-metal bonds; and a device layer on the second bonding layer, the device layer including a contact and a transistor, the transistor including a first source/drain region, the contact connecting a back-side of the first source/drain region to the second die connector.
Inventor(s): Wen-Shiang LIAO of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/64
Abstract: a semiconductor structure is provided. the semiconductor structure includes a substrate, a first conductive layer formed on the substrate, a chip disposed on the substrate, a first dielectric layer surrounding the chip, a second conductive layer disposed on the first dielectric layer and electrically insulated from the first conductive layer, a plurality of first vias formed in the first dielectric layer and electrically connected to the first conductive layer, and a plurality of second vias formed in the first dielectric layer and electrically connected to the second conductive layer. the first vias are arranged in a first direction. the second vias are arranged in the first direction, and the first vias and the second vias are arranged in a staggered fashion in a second direction, which is different from the first direction.
Inventor(s): Chih-Wei WU of Zhuangwei Township (TW) for taiwan semiconductor manufacturing co., ltd., An-Jhih SU of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Hua-Wei TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Ching SHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih CHIOU of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Wei CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ming Shih YEH of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng WU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang YEH of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/498, H01L23/538, H01L25/00, H01L25/10
Abstract: some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. the stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. the stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. the one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.
Inventor(s): Hao-Lin Yang of Kaohsiung CIty (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Chun Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Hui Tseng of Tainan CIty (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/522, H01L25/065
Abstract: a bonding structure that may be used to form 3d-ic devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. the first and second oblong bonding pads are laid crosswise, and the bond is formed. viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. the oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.
Inventor(s): Yi-Jung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen Chiang YU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-An TSAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Fu TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Szu-Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Shi LIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00
Abstract: a semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. the conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85�, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.
Inventor(s): Hung-Pin Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Shih Yeh of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/31, H01L23/498
Abstract: a semiconductor package includes a first semiconductor substrate, an array of conductive bumps, a second semiconductor substrate, and a spacing pattern. the first semiconductor substrate includes a pad region and an array of first pads disposed within the pad region. the array of conductive bumps is disposed on the array of first pads respectively. the second semiconductor substrate is disposed over the first semiconductor substrate and includes an array of second pads bonded to the array of conductive bumps respectively. the spacing pattern is disposed between the first semiconductor substrate and the second semiconductor substrate, wherein the spacing pattern is located at a periphery of the pad region.
Inventor(s): Fu Wei Liu of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Wei Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Chung Wu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Bo-Yu Chiu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Szu-Hsien Lee of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Mirng-Ji Lii of Sinpu Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L25/00, H01L29/02
Abstract: semiconductor devices and methods of manufacturing the semiconductor devices are presented. in embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. the first bonding layer and the semiconductor substrate are patterned to form first openings. a second substrate is bonded to the first substrate. after the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. after the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.
20240128232.SEMICONDUCTOR PACKAGE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Fu Su of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Cheng Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Wei Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hsun Lee of Hsin-chu County (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Yu Pan of Taipei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L23/31, H01L23/538, H01L25/00
Abstract: a semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. the first semiconductor die includes a conductive post in a protective layer. the encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. the high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. the redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. the protective layer is made of a fourth material, and a ratio of a young's modulus of the second material to a young's modulus of the fourth material is at least 1.5.
Inventor(s): Fu-Chiang KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsin Fang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Min-Hsiung Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/08, H01L21/3213, H01L21/48, H01L21/56, H01L21/66, H01L23/31, H01L23/498
Abstract: a structure and method for improving manufacturing yield of passive device dies are disclosed. the structure includes first and second groups of capacitors disposed on a substrate, an interconnect structure disposed on the first and second groups of capacitors, first and second bonding structures disposed on the first and second conductive lines, respectively, and first and second measurement structures connected to the first and second conductive lines, respectively, and configured to measure electrical properties of the first and second groups of capacitors, respectively. the interconnect structure includes first and second conductive line connected to the first and second groups of trench capacitors, respectively. the first bonding structure is electrically connected to the first group of capacitors and the second bonding structure is electrically isolated from the first and second groups of capacitors. the first and second measurement structures are electrically isolated from each other.
Inventor(s): Chun-Sheng Liang of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-San Chien of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pin Chun Shen of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chiang Hong of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Wing Yeung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. the first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. the second semiconductor structure includes a second gate structure wrapping around third sheet structures. the first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. the second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure. the first isolation block has an extending depth smaller than an extending depth of the second isolation block.
Inventor(s): Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01G4/30
Abstract: semiconductor devices and methods of forming the same are provided. in one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.
Inventor(s): Chun-Ming LUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Ting KO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Hsiang CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-En LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chi On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/40, H01L29/423, H01L29/66
Abstract: a semiconductor device includes a fin structure, a metal gate stack, a barrier structure and an epitaxial source/drain region. the fin structure is over a substrate. the metal gate stack is across the fin structure. the barrier structure is on opposite sides of the metal gate stack. the barrier structure comprises one or more passivation layers and one or more barrier layers, and the one or more passivation layers have a material different from a material of the one or more barrier layers. the epitaxial source/drain region is over the barrier structure.
Inventor(s): Chun-Yi CHANG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yu Ying CHEN of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Zhen-Cheng WU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chi On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L27/088, H01L29/66
Abstract: a method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ild) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ild layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to nh-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to n-terminated, while leaving the surfaces of the bottom portion of the trench being nh-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.
Inventor(s): Shih-Chiang Chen of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L27/088, H01L29/08, H01L29/423, H01L29/49, H01L29/66, H01L29/786
Abstract: a device a includes a substrate, two source/drain (s/d) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two s/d features. the device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the s/d features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.
Inventor(s): Yi-Cheng Chu of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hua Huang of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L29/40, H01L29/417, H01L29/423, H01L29/66
Abstract: a semiconductor device includes a first transistor and a protection structure. the first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. the protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. the protection structure includes a first capping layer and a dielectric portion. the first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. the dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.
Inventor(s): Yung-Ping Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Wen Shih of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shou-Zen Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Albert Wan of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Sheng Hsieh of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01Q1/22, H01L21/768, H01L23/00, H01L23/31, H01L23/48, H01L23/528, H01L23/66, H01Q1/38, H01Q9/04, H01Q21/06
Abstract: sensor packages and manufacturing methods thereof are disclosed. one of the sensor packages includes a semiconductor chip and a redistribution layer structure. the semiconductor chip has a sensing surface. the redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
20240128955.FLIP-FLOP CELL_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Shao-Yu Steve Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Te Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Chih Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Nick Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/037, G06F1/04
Abstract: an integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. the circuit elements are defined by standard layout cells selected from a cell library. the circuit elements including a plurality of flip-flops. each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. a first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.
Inventor(s): Jing DING of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Zhang-Ying YAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lei PAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/037, G06F30/392, H03K19/0185
Abstract: an integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. the input circuit includes a first set of transistors having a first threshold voltage. the first set of transistors includes a first set of active regions extending in a first direction. the level shifter circuit includes a second set of transistors having a second threshold voltage. the second set of transistors includes a second set of active regions extending in the first direction.
Inventor(s): Gerben DOORNBOS of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
Abstract: a static random access memory and a manufacturing method thereof are provided. the static random access memory includes a first complementary field effect transistor (cfet), a second cfet, a first pass fate transistor and a second pass gate transistor. the first cfet and the second cfet are disposed in a first tier. the first pass gate transistor is connected to the first cfet through a first path. the second pass gate transistor is connected to the second cfet through a second path. the first pass gate transistor and the second pass gate transistor are disposed in a second tier.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jer-Fu Wang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Tse Hung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Iuliana Radu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
Abstract: a memory device is provided. the memory device includes a write pass-gate transistor, a read pass-gate transistor, a write word line, and a read word line. the write pass-gate transistor is disposed in a first layer. the read pass-gate transistor is disposed in a second layer above the first layer. the write word line is disposed in a metallization layer above the first layer and electrically coupled to the write pass-gate transistor through a write path. the read word line is disposed in the metallization layer and electrically coupled to the read pass-gate transistor through a read path. the write path is different from the read path.
Inventor(s): Tsung-Hsueh Yang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/20, H10N70/00
Abstract: the present disclosure is directed towards an integrated chip including a heater structure overlying a semiconductor substrate. a phase change element (pce) is disposed over the heater structure. a thermal barrier structure is disposed between the heater structure and the pce. outer sidewalls of the pce are spaced laterally between outer sidewalls of the thermal barrier structure.
Taiwan Semiconductor manufacturing Co., Ltd. patent applications on April 18th, 2024
- Taiwan Semiconductor manufacturing Co., Ltd.
- B81C1/00
- B81B7/00
- Taiwan semiconductor manufacturing co., ltd.
- G01N21/95
- G01N21/59
- G03F7/038
- G03F7/20
- H01L21/027
- H01L21/768
- G06F30/398
- G06F30/392
- G06F30/394
- G11C13/00
- H01L21/67
- H01L21/677
- H01L21/302
- H01L21/48
- H01L21/56
- H01L21/762
- H01L23/538
- H01L23/48
- H01L25/10
- H01L21/8234
- H01L29/06
- H01L29/423
- H01L29/66
- H01L21/033
- H01L21/308
- H01L27/088
- H01L29/78
- H01L23/31
- H01L21/78
- H01L23/00
- H01L23/367
- H01L23/373
- H10B80/00
- H01L23/498
- H01L25/065
- H01L23/29
- H01L21/82
- H01L23/64
- H01L25/00
- H01L23/522
- H01L29/02
- H01L27/08
- H01L21/3213
- H01L21/66
- H01L27/092
- H01L21/8238
- H01L29/775
- H01G4/30
- H01L29/40
- H01L29/08
- H01L29/49
- H01L29/786
- H01L29/417
- H01Q1/22
- H01L23/528
- H01L23/66
- H01Q1/38
- H01Q9/04
- H01Q21/06
- H03K3/037
- G06F1/04
- H03K19/0185
- H10B10/00
- H10N70/20
- H10N70/00
- H01L24/08
