Difference between revisions of "Taiwan Semiconductor Manufacturing Company Limited patent applications published on November 30th, 2023"

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'''Summary of the patent applications from Taiwan Semiconductor Manufacturing Company Limited on November 30th, 2023'''
 
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Taiwan Semiconductor Manufacturing Company Limited (TSMC) has recently filed several patents related to various aspects of semiconductor technology. These patents cover methods for creating dielectric isolation layers, memory structures, enhancing charge carrier mobility, eliminating the need for read assist circuits, and fabricating transistors and capacitors. Notable applications of these patents include the creation of a dielectric isolation layer with electrodes and a phase change material (PCM) line, the development of a memory structure with multiple types of memory arrays and peripheral circuit devices, and the enhancement of charge carrier mobility in semiconducting material layers. Additionally, TSMC's patents describe devices and methods for eliminating the need for read assist circuits in semiconductor devices, as well as the fabrication of transistors and capacitors with specific design features. These patents demonstrate TSMC's commitment to advancing semiconductor technology and improving the performance and functionality of electronic devices.
 
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Summary of patents filed by TSMC:
 
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* Methods for creating dielectric isolation layers with electrodes and phase change material lines.
 
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* Memory structures with multiple types of memory arrays and peripheral circuit devices.
 
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* Methods for enhancing charge carrier mobility in semiconducting material layers.
 
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* Devices and methods for eliminating the need for read assist circuits in semiconductor devices.
 
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* Fabrication of transistors and capacitors with specific design features.
 
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Notable applications of TSMC's patents:
 
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* Creation of dielectric isolation layers with electrodes and phase change material lines.
 
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* Development of memory structures with multiple types of memory arrays and peripheral circuit devices.
 
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* Enhancement of charge carrier mobility in semiconducting material layers.
 
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* Elimination of the need for read assist circuits in semiconductor devices.
 
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* Fabrication of transistors and capacitors with specific design features.
 
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==Patent applications for Taiwan Semiconductor Manufacturing Company Limited on November 30th, 2023==
 
==Patent applications for Taiwan Semiconductor Manufacturing Company Limited on November 30th, 2023==
  
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===Systems and Methods for Classifying PUF Signature Modules of Integrated Circuits ([[US Patent Application 18446838. Systems and Methods for Classifying PUF Signature Modules of Integrated Circuits simplified abstract|18446838]])===
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===Systems and Methods for Classifying PUF Signature Modules of Integrated Circuits ([[US Patent Application 18446838. Systems and Methods for Classifying PUF Signature Modules of Integrated Circuits simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18446838]])===
  
  
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===Mixed Poly Pitch Design Solution for Power Trim ([[US Patent Application 18361948. Mixed Poly Pitch Design Solution for Power Trim simplified abstract|18361948]])===
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===Mixed Poly Pitch Design Solution for Power Trim ([[US Patent Application 18361948. Mixed Poly Pitch Design Solution for Power Trim simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18361948]])===
  
  
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===INTEGRATED CHIP PACKAGE INCLUDING A CRACK-RESISTANT LID STRUCTURE AND METHODS OF FORMING THE SAME ([[US Patent Application 17898834. INTEGRATED CHIP PACKAGE INCLUDING A CRACK-RESISTANT LID STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract|17898834]])===
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===INTEGRATED CHIP PACKAGE INCLUDING A CRACK-RESISTANT LID STRUCTURE AND METHODS OF FORMING THE SAME ([[US Patent Application 17898834. INTEGRATED CHIP PACKAGE INCLUDING A CRACK-RESISTANT LID STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|17898834]])===
  
  
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===PACKAGING SUBSTRATE INCLUDING A STRESS-ABSORPTION TRENCH AND METHODS OF FORMING THE SAME ([[US Patent Application 17828064. PACKAGING SUBSTRATE INCLUDING A STRESS-ABSORPTION TRENCH AND METHODS OF FORMING THE SAME simplified abstract|17828064]])===
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===PACKAGING SUBSTRATE INCLUDING A STRESS-ABSORPTION TRENCH AND METHODS OF FORMING THE SAME ([[US Patent Application 17828064. PACKAGING SUBSTRATE INCLUDING A STRESS-ABSORPTION TRENCH AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|17828064]])===
  
  
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===SEMICONDUCTOR PACKAGE INCLUDING LID WITH INTEGRATED HEAT PIPE FOR THERMAL MANAGEMENT AND METHODS FOR FORMING THE SAME ([[US Patent Application 18366788. SEMICONDUCTOR PACKAGE INCLUDING LID WITH INTEGRATED HEAT PIPE FOR THERMAL MANAGEMENT AND METHODS FOR FORMING THE SAME simplified abstract|18366788]])===
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===SEMICONDUCTOR PACKAGE INCLUDING LID WITH INTEGRATED HEAT PIPE FOR THERMAL MANAGEMENT AND METHODS FOR FORMING THE SAME ([[US Patent Application 18366788. SEMICONDUCTOR PACKAGE INCLUDING LID WITH INTEGRATED HEAT PIPE FOR THERMAL MANAGEMENT AND METHODS FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18366788]])===
  
  
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===SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAME ([[US Patent Application 18230135. SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAME simplified abstract|18230135]])===
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===SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAME ([[US Patent Application 18230135. SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18230135]])===
  
  
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===REDISTRIBUTION STRUCTURE WITH COPPER BUMPS ON PLANAR METAL INTERCONNECTS AND METHODS OF FORMING THE SAME ([[US Patent Application 17826223. REDISTRIBUTION STRUCTURE WITH COPPER BUMPS ON PLANAR METAL INTERCONNECTS AND METHODS OF FORMING THE SAME simplified abstract|17826223]])===
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===REDISTRIBUTION STRUCTURE WITH COPPER BUMPS ON PLANAR METAL INTERCONNECTS AND METHODS OF FORMING THE SAME ([[US Patent Application 17826223. REDISTRIBUTION STRUCTURE WITH COPPER BUMPS ON PLANAR METAL INTERCONNECTS AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|17826223]])===
  
  
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===SEMICONDUCTOR PACKAGE WITH VARIABLE PILLAR HEIGHT AND METHODS FOR FORMING THE SAME ([[US Patent Application 17828066. SEMICONDUCTOR PACKAGE WITH VARIABLE PILLAR HEIGHT AND METHODS FOR FORMING THE SAME simplified abstract|17828066]])===
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===SEMICONDUCTOR PACKAGE WITH VARIABLE PILLAR HEIGHT AND METHODS FOR FORMING THE SAME ([[US Patent Application 17828066. SEMICONDUCTOR PACKAGE WITH VARIABLE PILLAR HEIGHT AND METHODS FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|17828066]])===
  
  
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===DIE CORNER REMOVAL FOR UNDERFILL CRACK SUPPRESSION IN SEMICONDUCTOR DIE PACKAGING ([[US Patent Application 18446554. DIE CORNER REMOVAL FOR UNDERFILL CRACK SUPPRESSION IN SEMICONDUCTOR DIE PACKAGING simplified abstract|18446554]])===
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===DIE CORNER REMOVAL FOR UNDERFILL CRACK SUPPRESSION IN SEMICONDUCTOR DIE PACKAGING ([[US Patent Application 18446554. DIE CORNER REMOVAL FOR UNDERFILL CRACK SUPPRESSION IN SEMICONDUCTOR DIE PACKAGING simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18446554]])===
  
  
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===VERTICAL SEMICONDUCTOR PACKAGE INCLUDING HORIZONTALLY STACKED DIES AND METHODS OF FORMING THE SAME ([[US Patent Application 18230147. VERTICAL SEMICONDUCTOR PACKAGE INCLUDING HORIZONTALLY STACKED DIES AND METHODS OF FORMING THE SAME simplified abstract|18230147]])===
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===VERTICAL SEMICONDUCTOR PACKAGE INCLUDING HORIZONTALLY STACKED DIES AND METHODS OF FORMING THE SAME ([[US Patent Application 18230147. VERTICAL SEMICONDUCTOR PACKAGE INCLUDING HORIZONTALLY STACKED DIES AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18230147]])===
  
  
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===Device with a High Efficiency Voltage Multiplier ([[US Patent Application 18447367. Device with a High Efficiency Voltage Multiplier simplified abstract|18447367]])===
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===Device with a High Efficiency Voltage Multiplier ([[US Patent Application 18447367. Device with a High Efficiency Voltage Multiplier simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18447367]])===
  
  
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===SEMICONDUCTOR ARRANGEMENT WITH ISOLATION STRUCTURE ([[US Patent Application 18232085. SEMICONDUCTOR ARRANGEMENT WITH ISOLATION STRUCTURE simplified abstract|18232085]])===
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===SEMICONDUCTOR ARRANGEMENT WITH ISOLATION STRUCTURE ([[US Patent Application 18232085. SEMICONDUCTOR ARRANGEMENT WITH ISOLATION STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18232085]])===
  
  
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===FERROELECTRIC MFM CAPACITOR ARRAY AND METHODS OF MAKING THE SAME ([[US Patent Application 18363217. FERROELECTRIC MFM CAPACITOR ARRAY AND METHODS OF MAKING THE SAME simplified abstract|18363217]])===
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===FERROELECTRIC MFM CAPACITOR ARRAY AND METHODS OF MAKING THE SAME ([[US Patent Application 18363217. FERROELECTRIC MFM CAPACITOR ARRAY AND METHODS OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18363217]])===
  
  
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===SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING ([[US Patent Application 18231847. SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING simplified abstract|18231847]])===
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===SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING ([[US Patent Application 18231847. SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18231847]])===
  
  
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===SELF-ALIGNED ACTIVE REGIONS AND PASSIVATION LAYER AND METHODS OF MAKING THE SAME ([[US Patent Application 18446541. SELF-ALIGNED ACTIVE REGIONS AND PASSIVATION LAYER AND METHODS OF MAKING THE SAME simplified abstract|18446541]])===
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===SELF-ALIGNED ACTIVE REGIONS AND PASSIVATION LAYER AND METHODS OF MAKING THE SAME ([[US Patent Application 18446541. SELF-ALIGNED ACTIVE REGIONS AND PASSIVATION LAYER AND METHODS OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18446541]])===
  
  
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===TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME ([[US Patent Application 18230864. TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME simplified abstract|18230864]])===
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===TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME ([[US Patent Application 18230864. TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18230864]])===
  
  
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===RAISED SOURCE/DRAIN OXIDE SEMICONDUCTING THIN FILM TRANSISTOR AND METHODS OF MAKING THE SAME ([[US Patent Application 18366725. RAISED SOURCE/DRAIN OXIDE SEMICONDUCTING THIN FILM TRANSISTOR AND METHODS OF MAKING THE SAME simplified abstract|18366725]])===
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===RAISED SOURCE/DRAIN OXIDE SEMICONDUCTING THIN FILM TRANSISTOR AND METHODS OF MAKING THE SAME ([[US Patent Application 18366725. RAISED SOURCE/DRAIN OXIDE SEMICONDUCTING THIN FILM TRANSISTOR AND METHODS OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18366725]])===
  
  
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===Semiconductor Device Including a Layer Between a Source/Drain Region and a Substrate ([[US Patent Application 18366733. Semiconductor Device Including a Layer Between a Source/Drain Region and a Substrate simplified abstract|18366733]])===
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===Semiconductor Device Including a Layer Between a Source/Drain Region and a Substrate ([[US Patent Application 18366733. Semiconductor Device Including a Layer Between a Source/Drain Region and a Substrate simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18366733]])===
  
  
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===MOBILITY ENHANCEMENT BY SOURCE AND DRAIN STRESS LAYER OR IMPLANTATION IN THIN FILM TRANSISTORS ([[US Patent Application 18446755. MOBILITY ENHANCEMENT BY SOURCE AND DRAIN STRESS LAYER OR IMPLANTATION IN THIN FILM TRANSISTORS simplified abstract|18446755]])===
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===MOBILITY ENHANCEMENT BY SOURCE AND DRAIN STRESS LAYER OR IMPLANTATION IN THIN FILM TRANSISTORS ([[US Patent Application 18446755. MOBILITY ENHANCEMENT BY SOURCE AND DRAIN STRESS LAYER OR IMPLANTATION IN THIN FILM TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18446755]])===
  
  
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===MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME ([[US Patent Application 18362192. MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME simplified abstract|18362192]])===
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===MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME ([[US Patent Application 18362192. MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|18362192]])===
  
  
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===ENCAPSULATED PHASE CHANGE MATERIAL SWITCH AND METHODS FOR FORMING THE SAME ([[US Patent Application 17826815. ENCAPSULATED PHASE CHANGE MATERIAL SWITCH AND METHODS FOR FORMING THE SAME simplified abstract|17826815]])===
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===ENCAPSULATED PHASE CHANGE MATERIAL SWITCH AND METHODS FOR FORMING THE SAME ([[US Patent Application 17826815. ENCAPSULATED PHASE CHANGE MATERIAL SWITCH AND METHODS FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)|17826815]])===
  
  

Revision as of 07:04, 5 December 2023

Contents

Patent applications for Taiwan Semiconductor Manufacturing Company Limited on November 30th, 2023

Systems and Methods for Classifying PUF Signature Modules of Integrated Circuits (18446838)

Main Inventor

Cheng-En Lee


Mixed Poly Pitch Design Solution for Power Trim (18361948)

Main Inventor

Shih-Wei Peng


INTEGRATED CHIP PACKAGE INCLUDING A CRACK-RESISTANT LID STRUCTURE AND METHODS OF FORMING THE SAME (17898834)

Main Inventor

Wensen Hung


PACKAGING SUBSTRATE INCLUDING A STRESS-ABSORPTION TRENCH AND METHODS OF FORMING THE SAME (17828064)

Main Inventor

Hsien-Wei Chen


SEMICONDUCTOR PACKAGE INCLUDING LID WITH INTEGRATED HEAT PIPE FOR THERMAL MANAGEMENT AND METHODS FOR FORMING THE SAME (18366788)

Main Inventor

Yu-Sheng LIN


SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAME (18230135)

Main Inventor

Jen-Yuan CHANG


REDISTRIBUTION STRUCTURE WITH COPPER BUMPS ON PLANAR METAL INTERCONNECTS AND METHODS OF FORMING THE SAME (17826223)

Main Inventor

Hsien-Wei Chen


SEMICONDUCTOR PACKAGE WITH VARIABLE PILLAR HEIGHT AND METHODS FOR FORMING THE SAME (17828066)

Main Inventor

Li-Ling Liao


DIE CORNER REMOVAL FOR UNDERFILL CRACK SUPPRESSION IN SEMICONDUCTOR DIE PACKAGING (18446554)

Main Inventor

Wei-Yu CHEN


VERTICAL SEMICONDUCTOR PACKAGE INCLUDING HORIZONTALLY STACKED DIES AND METHODS OF FORMING THE SAME (18230147)

Main Inventor

Jen-Yuan CHANG


Device with a High Efficiency Voltage Multiplier (18447367)

Main Inventor

Yu-Tso Lin


SEMICONDUCTOR ARRANGEMENT WITH ISOLATION STRUCTURE (18232085)

Main Inventor

Feng-Chien HSIEH


FERROELECTRIC MFM CAPACITOR ARRAY AND METHODS OF MAKING THE SAME (18363217)

Main Inventor

Chun-Chieh LU


SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING (18231847)

Main Inventor

Shih-Wei PENG


SELF-ALIGNED ACTIVE REGIONS AND PASSIVATION LAYER AND METHODS OF MAKING THE SAME (18446541)

Main Inventor

Hung Wei LI


TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME (18230864)

Main Inventor

Hung Wei LI


RAISED SOURCE/DRAIN OXIDE SEMICONDUCTING THIN FILM TRANSISTOR AND METHODS OF MAKING THE SAME (18366725)

Main Inventor

Gerben Doornbos


Semiconductor Device Including a Layer Between a Source/Drain Region and a Substrate (18366733)

Main Inventor

Kam-Tou Sio


MOBILITY ENHANCEMENT BY SOURCE AND DRAIN STRESS LAYER OR IMPLANTATION IN THIN FILM TRANSISTORS (18446755)

Main Inventor

Hui-Hsien WEI


MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME (18362192)

Main Inventor

Chao-I WU


ENCAPSULATED PHASE CHANGE MATERIAL SWITCH AND METHODS FOR FORMING THE SAME (17826815)

Main Inventor

Tsung-Hsueh Yang

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