Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on September 28th, 2023

HYBRID ULTRASONIC TRANSDUCER SYSTEM (17832937)

Abstract

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a dielectric stack disposed on a substrate. The integrated chip structure further includes one or more piezoelectric ultrasonic transducers (PMUTs) and one or more capacitive ultrasonic transducers (CMUTs). The one or more PMUTs include a piezoelectric stack disposed within the dielectric stack over one or more PMUT cavities. The one or more CMUTs include electrodes disposed within the dielectric stack and separated by one or more CMUT cavities. An isolation chamber is arranged within the dielectric stack laterally between the one or more PMUTs and the one or more CMUTs. The isolation chamber vertically extends past at least a part of both the one or more PMUTs and the one or more CMUTs.

Inventor

Ching-Hui Lin

EUV PHOTO MASKS AND MANUFACTURING METHOD THEREOF (17833823)

Abstract

A photo mask for an extreme ultraviolet (EUV) lithography includes a mask alignment mark for aligning the photo mask to an EUV lithography tool, and sub-resolution assist patterns disposed around the mask alignment mark. A dimension of the sub-resolution assist patterns is in a range from 10 nm to 50 nm.

Inventor

Wei-Shuo SU

METHOD OF LITHOGRAPHY PROCESS AND TRANSFERRING A RETICLE (18326210)

Abstract

A method of lithography process is provided. The method includes forming a conductive layer over a reticle. The method includes applying ionized particles to the reticle by a discharging device. The method includes forming a photoresist layer over a semiconductor substrate. The method includes securing the semiconductor substrate by a wafer electrostatic-clamp. The method also includes patterning the photoresist layer by emitting radiation from a radiation source via the reticle.

Inventor

Hsiao-Lun CHANG

PROGRAMMING CIRCUIT, INTEGRATED CIRCUIT, AND METHOD (17703889)

Abstract

A programming circuit includes a time difference converter circuit and a pulse generator circuit. The converter circuit is configured to receive a first pulse from a first neuron device and a second pulse from a second neuron device, and to output a time difference signal corresponding to a time difference between the first pulse and the second pulse. The pulse generator circuit includes an input coupled to the output of the time difference converter circuit to receive the time difference signal, and an output at which the pulse generator circuit is configured to output a program voltage corresponding to the time difference signal. The output of the pulse generator circuit is configured to be coupled to a synapse device coupled between the first neuron device and the second neuron device to program a weight value in the synapse device with the program voltage.

Inventor

Jen-Chieh LIU

SEMICONDUCTOR MEMORY DEVICES WITH DIODE-CONNECTED MOS (18328110)

Abstract

A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Inventor

Perng-Fei Yuh

SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE AND METHOD FOR FORMING (18328102)

Abstract

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Inventor

Cheng-Ta Wu

WET ETCHING CHEMISTRY AND METHOD OF FORMING SEMICONDUCTOR DEVICE USING THE SAME (17703997)

Abstract

A wet etching chemistry to selectively remove a polymer residue on an opening embedded in a low-k dielectric layer and an underlying stop layer in a process of forming an interconnect structure is provided. The wet etching chemistry includes: two type of organic solvents, wherein a concentration of the two type of organic solvents is greater than or equal to 70%; an Alkali source amine, at least comprising a tertiary amine; an inhibitor; and water. In some embodiment, the wet etching chemistry is free of a peroxide to avoid damage to the WdC hard mask.

Inventor

Meng-Hsien Li

PICK-AND-PLACE SYSTEM WITH A STABILIZER (17700497)

Abstract

A pick-and-place system is provided. The pick-and-place system includes: a wafer holder configured to hold a bottom die; a gantry having a stabilizer extending downwardly; a primary drive mechanism connected to the gantry and configured to drive the gantry horizontally and vertically; a suction head configured to hold a top die; and a secondary drive mechanism located at the gantry and connected to the suction head and configured to drive the suction head horizontally and vertically to place the top die on the bottom die at a target position. The primary drive mechanism drives the gantry vertically until the stabilizer is in contact with the bottom die before the secondary drive mechanism drives the suction head.

Inventor

Jen-Yuan Chang

STRUCTURE AND METHOD FOR FINFET DEVICE WITH SOURCE/DRAIN MODULATION (18321188)

Abstract

The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate with a first circuit area and a second circuit area; forming a first active region within the first circuit area and a second active region within the second circuit area; forming a first gate structure on the first active region and a second gate structure on the second active region; introducing a doping species to the first active region but not the second active region; performing an etching process, thereby simultaneously recessing both first source/drain regions of the first active region and second source/drain regions of the second active region at a same etch rate; and thereafter, epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

Inventor

Ta-Chun Lin

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME (18327030)

Abstract

A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

Inventor

Jung-Wei Cheng

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (17702820)

Abstract

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes first semiconductor dies spaced apart from one another, second semiconductor dies stacked upon the first semiconductor dies with a one-to-one correspondence and electrically coupled to the first semiconductor dies, a first composite structure laterally interposed between two first semiconductor dies, a second composite structure laterally interposed between two second semiconductor dies, and a support substrate bonded to the second semiconductor dies and the second composite structure. The first composite structure includes a first material layer adjoining sidewalls of the two first semiconductor dies and a second material layer connected to and different from the first material layer. The second composite structure includes a third material layer adjoining sidewalls of the two second semiconductor dies and a fourth material layer connected to and different from the third material layer.

Inventor

Ming-Fa Chen

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18321739)

Abstract

Semiconductor device includes a circuit substrate, a first semiconductor die and a package lid. The first semiconductor die is disposed on and electrically connected to the circuit substrate. The package lid extends over the first semiconductor die and is bonded to the circuit substrate. the package lid comprises a roof extending, a footing and an island. The roof extends along a first direction and a second direction perpendicular to the first direction. The footing is disposed at a peripheral edge of the roof and protrudes from the roof towards the circuit substrate along a third direction perpendicular to the first direction and the second direction. The island protrudes from the roof towards the circuit substrate, wherein the island is disconnected from the footing along the second direction, and the island is physically connected to the footing along the first direction.

Inventor

Shu-Shen Yeh

BACKSIDE LEAKAGE PREVENTION (17824391)

Abstract

A package structure according to the present disclosure includes a bottom substrate, a bottom interconnect structure over the bottom substrate, a top interconnect structure disposed over the bottom interconnect structure and including a metal feature, a top substrate over the top interconnect structure, and a protective film disposed on the top substrate. The protective film includes an interfacial layer on the top substrate, at least one dipole-inducing layer on the interfacial layer, a moisture block layer on the at least one dipole-inducing layer, and a silicon oxide layer over the moisture block layer. The at least one dipole-inducing layer includes aluminum oxide, titanium oxide or zirconium oxide.

Inventor

Harry-Haklay Chuang

THREE-DIMENSIONAL INTEGRATED STRUCTURE AND MANUFACTURING METHOD THEREOF (17704026)

Abstract

A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

Inventor

Yun-Feng Kao

ONE-TIME-PROGRAMMABLE DEVICE STRUCTURE (17703710)

Abstract

a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.

Inventor

Yu-Hsiang Chen

BACKSIDE SIGNAL INTERCONNECTION (18319593)

Abstract

A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Inventor

Yu-Xuan Huang

REDISTRIBUTION LAYER FEATURES (18328916)

Abstract

Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

Inventor

Wen-Chun Wang

CHIP PACKAGE STRUCTURE (18319610)

Abstract

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar between the first chip structure and the second chip structure. In addition, the chip package structure includes an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate. A topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar.

Inventor

Jiun-Ting CHEN

PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF (18327076)

Abstract

A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

Inventor

Kuan-Yu Huang

SEMICONDUCTOR PACKAGE WITH HIGH DENSITY OF THROUGH-SILICON VIAS (TSV) (17702765)

Abstract

A semiconductor die is provided. The semiconductor die includes: a silicon substrate; a bonding layer formed at a back side of the silicon substrate and including a first metal pad; a multi-layer interconnect (MLI) structure formed at a front side of the silicon substrate; a first through-silicon via (TSV) penetrating the silicon substrate and at least a portion of the MLI structure in a vertical direction, wherein a first end of the first TSV is in contact with and electrically connected to the first metal pad, and a second end of the first TSV is electrically connected to a first metal track located in the MLI structure; and a first guard ring formed in the MLI structure, wherein the first guard ring extends in the vertical direction and surrounds the first TSV, and the first guard ring is electrically connected to the first metal track.

Inventor

Jen-Yuan Chang

SEMICONDUCTOR PACKAGE (18325136)

Abstract

A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Inventor

Chi-Yang Yu

BOUNDARY CELLS ADJACENT TO KEEP-OUT ZONES (17721246)

Abstract

An integrated circuit includes an array of first-type active-region structures and an array of second-type active-region structures extending in a first direction between a first vertical zone-boundary of a first keep-out zone and the second vertical zone-boundary of a second keep-out zone. The integrated circuit also includes an array of first-side boundary cells aligned with the first vertical zone-boundary and an array of second-side boundary cells aligned with the second vertical zone-boundary. In the array of first-side boundary cells, a first-side boundary cell has a first ESD protection circuit and a pick-up region. In the array of second-side boundary cells, a second-side boundary cell has a second ESD protection circuit.

Inventor

Jia Liang ZHONG

DEEP TRENCH CAPACITOR (DTC) REGION IN SEMICONDUCTOR PACKAGE (17701580)

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate and a deep trench capacitor (DTC) region formed in the substrate. The DTC region includes a plurality of DTC units, and each DTC unit includes: a trench extending downwardly from a top surface of the substrate; a first conductive layer disposed in the trench; a second conductive layer disposed in the trench; and a dielectric layer sandwiched by the first conductive layer and the second conductive layer. Each DTC unit is elongated, and a first group of the plurality of DTC units extend horizontally in a first direction, whereas a second group of the plurality of the DTC units extend horizontally in a second direction.

Inventor

Fu-Chiang Kuo

SEMICONDUCTOR DEVICE HAVING ANTENNA AND MANUFACTURING METHOD THEREOF (18325003)

Abstract

A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

Inventor

Albert Wan

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF (17705385)

Abstract

A package structure includes a die, a first redistribution circuit structure, a first redistribution circuit structure, a second redistribution circuit structure, an enhancement layer, first conductive terminals, and second conductive terminals. The first redistribution circuit structure is disposed on a rear side of the die and electrically coupled to thereto. The second redistribution circuit structure is disposed on an active side of the die and electrically coupled thereto. The enhancement layer is disposed on the first redistribution circuit structure. The first redistribution circuit structure is disposed between the enhancement layer and the die. The first conductive terminals are connected to the first redistribution circuit structure. The first redistribution circuit structure is between the first conductive terminals and the die. The second conductive terminals are connected to the second redistribution circuit structure. The enhancement layer is between the second conductive terminals and the second redistribution circuit structure.

Inventor

Cheng-Yu Kuo

PACKAGE (18327851)

Abstract

A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

Inventor

Sung-Feng Yeh

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME (17858387)

Abstract

A method of manufacturing a semiconductor structure includes following operations: moving a die towards a wafer by a pick-and-place tool, the pick-and-place tool including an infrared (IR) detection device attached to the pick-and-place tool in a fixed relationship; aligning the die with the wafer by using the IR detection device; and bonding the die to the wafer.

Inventor

Jen-Yuan Chang

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME (18305370)

Abstract

A semiconductor structure includes a first die, a dielectric layer, a second interconnection structure, a second conductive pad and a conductive feature. The first die includes a first interconnection structure over a first substrate and a first conductive pad disposed on and electrically connected to the first interconnection structure. The first conductive pad has a probe mark on a surface thereof. The dielectric layer laterally warps around the first die. The second interconnection structure is disposed on the first die and the dielectric layer, the second interconnection structure includes a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark. The second conductive pad is disposed on and electrically connected to the second interconnection structure. The conductive feature is disposed on the second conductive pad.

Inventor

Ming-Fa Chen

SEMICONDUCTOR PACKAGE WITH ENHANCED BONDING FORCE (17702764)

Abstract

A semiconductor package is provided. The semiconductor package includes: a bottom die having a first bonding layer formed at a top surface of the bottom die; a top die on the bottom die, wherein the top die comprises a second bonding layer formed at a bottom surface of the top die, and the top die is bonded to the bottom die by bonding the first bonding layer and the second bonding layer using hybrid bonding; a dummy die on the bottom die and lateral to the top die, wherein the dummy die comprises a third bonding layer formed at a bottom surface of the dummy die, and the dummy die is bonded to the bottom die by bonding the first bonding layer and the third bonding layer; and at least one dummy metal pad formed in one of the first bonding layer and the third bonding layer and not electrically connected.

Inventor

Jen-Yuan Chang

Novel Protection Diode Structure For Stacked Image Sensor Devices (17845624)

Abstract

A first side of a sensor wafer is bonded to a first side of a first logic wafer. The sensor wafer contains pixels configured to detect radiation that enters the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer contains circuitry configured to operate the pixels. The sensor wafer or the first logic wafer contains a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. A through-substrate-via (TSV) is formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from being damaged during the forming of the TSV. The second side of the first logic wafer is bonded to a second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

Inventor

Min-Feng Kao

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (17871451)

Abstract

A semiconductor device having a standard cell comprises a first bottom transistor, a first top transistor, a second bottom transistor, a second top transistor, and a first bottom-transistor-level metal line. The first bottom transistor is in a first row. The first top transistor is disposed above the first bottom transistor in the first row. The first bottom transistor and the first top transistor share a first gate structure. The second bottom transistor is in a second row next to the first row. The second top transistor is disposed above the second bottom transistor in the second row. The second bottom transistor and the second top transistor share a second gate structure. The first bottom-transistor-level metal line extends laterally from a first source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.

Inventor

Wei-Cheng KANG

IMAGE SENSOR HAVING AN IMPROVED STRUCTURE FOR SMALL PIXEL DESIGNS (17832905)

Abstract

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a substrate having a first side and a second side. The substrate includes a pixel region. A photodetector is in the pixel region. A first doped region is in the pixel region. A second doped region is in the pixel region. The second doped region is vertically between the first doped region and the first side of the substrate. A doped well is in the substrate and laterally surrounds the pixel region. The doped well is partially in the second doped region. A portion of the second doped region is vertically between the doped well and the second side of the substrate. A trench isolation structure is in the semiconductor substrate and laterally surrounds the pixel region. A footprint of the trench isolation structure is within a footprint of the doped well.

Inventor

Yen-Yu Chen

METAL-INSULATOR-METAL DEVICE CAPACITANCE ENHANCEMENT (17703150)

Abstract

In some embodiments, the present application provides an integrated chip (IC). The IC includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a plurality of conductive plates that are spaced from one another. The MIM device further includes a first conductive plug structure that is electrically coupled to a first conductive plate and to a third conductive plate of the plurality of conductive plates. A first plurality of insulative segments electrically isolate a second conductive plate and a fourth conductive plate from the first conductive plug structure. The MIM device further includes a second conductive plug structure that is electrically coupled to the second conductive plate and to the fourth conductive plate of the plurality of conductive plates. A second plurality of insulative segments electrically isolate the first conductive plate and the third conductive plate from the second conductive plug structure.

Inventor

Lu-Sheng Chou

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES (18130296)

Abstract

A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Inventor

Cheng-Yi PENG

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE STACK (17701997)

Abstract

A semiconductor device structure and a formation method are provided. The method includes forming a channel structure over a substrate and forming a dielectric layer over the channel structure. The dielectric layer has a higher dielectric constant greater than silicon nitride. The method also includes forming a gate stack over the dielectric layer and forming a spacer element over a sidewall of the gate stack. The spacer element covers a portion of the dielectric layer.

Inventor

Pin-Chun SHEN

SEMICONDUCTOR DEVICE INCLUDING TRANSMISSION LINES AND METHOD OF FORMING THE SAME (18312202)

Abstract

A method of making a semiconductor device includes forming a first transmission line over a substrate. The method includes forming a second transmission line over the substrate. The method further includes depositing a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material partially covers each of the first transmission line and the second transmission line. The method further includes depositing a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material directly contacts the first transmission line or the second transmission line.

Inventor

Jiun Yi WU

WDM CHANNEL REASSIGNMENT (17888947)

Abstract

An optical device includes a first waveguide, ring-shaped waveguides adjacent to the first waveguide, and heaters coupled to the ring-shaped waveguides in one-to-one correspondence. A method includes coupling a first light source with a first wavelength to the first waveguide, increasing electric current through the heaters until a first one of the ring-shaped waveguides resonates, assigning the first one of the ring-shaped waveguides to the first wavelength, resetting the electric current through the heaters to the initial electric current, coupling a second light source with a second wavelength to the first waveguide wherein the second wavelength is different from the first wavelength, increasing the electric current through the heaters until a second one of the ring-shaped waveguides resonates wherein the second one of the ring-shaped waveguides is different from the first one of the ring-shaped waveguides, and assigning the second one of the ring-shaped waveguides to the second wavelength.

Inventor

Chih-Chang Lin

IMAGE SENSOR INCLUDING LIGHT SHIELDING LAYER AND PATTERNED DIELECTRIC LAYER (18327825)

Abstract

An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.

Inventor

Yun-Wei Cheng

SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (17655918)

Abstract

Some implementations described herein incorporate a heating system to heat a cover of a bucket. A liquified target material, collected by vanes and/or a transport ring within a vessel of an extreme ultraviolet (EUV) radiation source, flows through a drain port of the transport ring and through a conduit that provides the liquified target material to the bucket through an opening of the cover. By heating the cover, the heating system prevents the liquified target material from solidifying at or near the opening before the liquified target material can flow into the bucket. By preventing the solidifying of the liquid target material, a likelihood of a blockage within the conduit and/or the drain port is reduced.

Inventor

Wei-Chun YEN

STATIC RANDOM-ACCESS MEMORY CELL, TRANSISTOR, AND METHOD THEREOF (17703931)

Abstract

A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.

Inventor

Hung-Li Chiang

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18325766)

Abstract

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

Inventor

Meng-Han Lin

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18324245)

Abstract

A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Inventor

Tzu-Yu CHEN

VERTICAL 1T1R STRUCTURE FOR EMBEDDED MEMORY (17701144)

Abstract

Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.

Inventor

Kuo-Pin Chang