Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on October 5th, 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on October 5th, 2023

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has filed several recent patents related to memory cells, integrated chips, non-volatile memory devices, semiconductor devices, memory and logic device optimization, laminated structures, analog-to-digital converting devices, and fabrication methods for semiconductor devices. These patents demonstrate TSMC's focus on advancing semiconductor technology and improving memory and logic devices.

Notable applications include:

• A resistive random-access memory (RRAM) cell with a barrier layer to prevent the movement of non-metal elements, reducing parasitic resistance.
• An integrated chip with multiple layers of interconnect dielectric material, a ferroelectric layer, and a sidewall portion connecting the lower and upper portions.
• A method to integrate non-volatile memory (NVM) devices with logic or BCD devices, involving forming an isolation structure and creating memory and peripheral device structures.
• A semiconductor device with a memory structure consisting of conductive lines, a channel element with an air gap, and memory elements for data storage.
• Methods and structures for optimizing the use of memory and logic devices, utilizing gate structures and source/drain features at different distances.
• A laminated structure with an interconnect substrate, encapsulant, and redistribution structure with protective patterns.
• An analog-to-digital converting device with multiple stages of ADCs, calibration circuits, a data recovery circuit, and an output circuit.
• A method and device involving a substrate with two transistor terminals connected by a non-linear via with a wave-like shape.
• A method for fabricating a semiconductor device, including forming a 2-D semiconductor layer, source/drain contacts, and a gate structure.
• A method of manufacturing a semiconductor device with a fin structure, sacrificial gate structure, isolation region, and void region for electrical isolation.

These recent patents demonstrate TSMC's commitment to innovation in semiconductor technology, particularly in memory cells, integrated chips, and fabrication methods. TSMC's focus on improving memory and logic devices through optimization and advanced structures highlights their dedication to advancing the semiconductor industry.

Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 5th, 2023

FACET PROFILE TO IMPROVE EDGE COUPLER BEAM POINTING AND COUPLING EFFICIENCY FOR PHOTONICS (17856382)

Inventor Wei-Kang Liu

Brief explanation

The abstract describes an integrated circuit that includes a substrate with an upper and lower face. The upper face has a central region and an outer sidewall surrounding it. An optical edge coupler is placed over the upper face, extending from the central region towards the outer sidewall. The optical edge coupler's outer sidewall matches the substrate's outer sidewall and has either a concave or convex surface.

Abstract

Various embodiments of the present disclosure are directed towards an integrated circuit. The integrated circuit includes a substrate having an upper face and a lower face. The upper face includes a central region and an outer sidewall that laterally surrounds the central region and that extends from the upper face to the lower face. An optical edge coupler is disposed over the upper face of the substrate and extends in a first direction from the central region toward the outer sidewall. An outer sidewall of the optical edge coupler corresponds to the outer sidewall of the substrate and has a concave surface or a convex surface.

OPTICAL DEVICE FOR COUPLING LIGHT AND METHOD FOR FABRICATING THE SAME (18331184)

Inventor Chan-Hong Chern

Brief explanation

The abstract describes an optical device that is used to connect a waveguide (a structure that guides light) to an optical transmission component. The device consists of two parts: a taper portion and a grating portion. The taper portion is located between the grating portion and the waveguide. The grating portion contains rows of grating patterns, which are patterns that manipulate the light. In each row, the size of the grating patterns varies, with the first pattern being larger than the second pattern. Additionally, the distance between the first row of grating patterns and the waveguide is smaller than the distance between the second row of grating patterns and the waveguide.

Abstract

An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.

EUV PHOTO MASKS AND MANUFACTURING METHOD THEREOF (17833830)

Inventor Sheng-Min WANG

Brief explanation

The abstract describes a photo mask used in extreme ultraviolet (EUV) lithography. The mask consists of a circuit pattern, which is the main pattern to be transferred onto a substrate, and sub-resolution assist patterns that are placed around and connected to the circuit pattern. These sub-resolution assist patterns are smaller in size, ranging from 10 nm to 50 nm. The purpose of these patterns is to improve the accuracy and quality of the circuit pattern during the lithography process.

Abstract

A photo mask for an extreme ultraviolet (EUV) lithography includes a circuit pattern, and sub-resolution assist patterns disposed around and connected to the circuit pattern. A dimension of the sub-resolution assist patterns is in a range from 10 nm to 50 nm.

METHOD FOR LITHOGRAPHY USING MIDDLE LAYER WITH POROUS TOP SURFACE (17710218)

Inventor Yuan Chih LO

Brief explanation

The method described in the abstract involves several steps. First, a middle layer is deposited on a substrate, and this middle layer contains sacrificial additives. Then, a heating process is carried out to cross-link the middle layer. During this process, the sacrificial additives float to the top surface of the middle layer. After the heating process, the sacrificial additives are removed from the middle layer. Next, a photoresist layer is deposited on top of the middle layer. This photoresist layer is then exposed to a radiation beam. Finally, the photoresist layer is developed after exposure to the radiation beam.

Abstract

A method includes depositing a middle layer over a substrate. The middle layer includes sacrificial additives. A heating process is performed to cross-link the middle layer. The sacrificial additives are floated onto a top surface of the middle layer. The sacrificial additives are removed from the middle layer after the heating process is performed. A photoresist layer is deposited over the middle layer. The photoresist layer is exposed to a radiation beam. The photoresist layer is developed after the photoresist layer is exposed.

PARTICLE REMOVING ASSEMBLY AND METHOD OF CLEANING MASK FOR LITHOGRAPHY (18200951)

Inventor Chen-Yang LIN

Brief explanation

The abstract describes a photolithographic apparatus that is used for removing particles from a mask used in the manufacturing of electronic devices. The apparatus includes a cassette with a slit that has a series of nozzles, which eject pressurized cleaning material onto the mask's surface to remove debris particles. The apparatus also has a pump and a compressor that are controlled by a controller to adjust the flow rate and pressure of the cleaning material based on the amount of debris particles on the mask's surface.

Abstract

A photolithographic apparatus includes a particle removing cassette, a pump and a compressor. The particle removing cassette includes a first slit that includes an array of parallel wind blade nozzles arranged along a length of the first slit, protruding from the first slit, and configured to eject and direct pressurized cleaning material to a patterning surface of a mask to remove debris particles on the patterning surface. The pump and the compressor are controlled by a controller to adjust a flow rate and a pressure of the pressurized cleaning material based on an amount of debris particles on the patterning surface of the mask.

COMPUTE-IN-MEMORY CELL (17855089)

Inventor Hidehiro Fujiwara

Brief explanation

This abstract describes a device that consists of multiple memory cells and logic elements. The first memory cell stores a first bit, while the second memory cell stores a second bit. The first logic element is connected to the first memory cell, and the second logic element is connected to the second memory cell. The third logic element is connected to the outputs of the first and second logic elements.

Abstract

A device includes a first memory cell, a second memory cell, a first logic element, a second logic element, and a third logic element. The first memory cell is configured to store a first bit at a first node, and the second memory cell is configured to store a second bit at a second node. The first logic element includes a first node input terminal coupled to the first node, the second logic element includes a second node input terminal coupled to the second node, and the third logic element includes a first input terminal coupled to a first output terminal of the first logic element and a second input terminal coupled to a second output terminal of the second logic element.

BOUNDARY CELL (18331576)

Inventor Yu-Jung Chang

Brief explanation

The abstract describes a method for designing circuits by placing boundary cells and dummy cells. The boundary cells are determined to define the circuit's boundary. Dummy cells of two different types are then placed along different portions of the boundary. Each type of dummy cell has predefined dimensions, and the dimensions of the second type of dummy cells are different from those of the first type.

Abstract

Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM (17821187)

Inventor Win-San KHWA

Brief explanation

This abstract describes a memory system and its operating method for performing computing-in-memory operations. The memory system consists of a memory array and a processing circuit. The memory array contains multiple memory cells, while the processing circuit includes a programming circuit and a control circuit. The programming circuit is responsible for programming the electrical characteristics of the memory cells through a write operation. The control circuit, on the other hand, receives a set of weight data corresponding to different weight values and controls the write operation in a sequential manner according to the order of these weight values.

Abstract

Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.

RESISTIVE MEMORY WITH ENHANCED REDUNDANCY WRITING (17709662)

Inventor Yu-Der Chih

Brief explanation

This abstract describes a memory device that consists of two arrays: a main array and a redundancy array. The main array contains memory cells, while the redundancy array contains backup memory cells. The device also includes write circuitry that performs programming operations on the main memory cells. During the first programming operation, the circuitry checks if the current of a main memory cell exceeds a specific threshold. If it does, the circuitry disables a second programming operation for a redundancy memory cell.

Abstract

A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

MEMORY SYSTEM WITH PHYSICAL UNCLONABLE FUNCTION (17710442)

Inventor Meng-Sheng CHANG

Brief explanation

The abstract describes a method for programming a physical unclonable function (PUF) in a memory device. The method involves programming a first bit of the PUF into a memory cell and generating a current that represents the logic value of the first bit. This programming process includes turning on certain switches in the memory circuit based on a bit line signal. The abstract also mentions a memory device and a system that utilize this method.

Abstract

A method includes: programming a first bit of a physical unclonable function into a first memory cell; and generating, by a first memory circuit in the first memory cell, a first current indicating a logic value of the first bit. The programming the first bit includes: turning on a first switch in the first memory circuit and at least one second switch in at least one second memory circuit in the first memory cell in response to a first bit line signal, to program one of the first memory circuit and the at least one second memory circuit while rest of the first memory circuit and the at least one second memory circuit is not programmed, according to the first bit line signal. A memory device and a system are also disclosed herein.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES (17840480)

Inventor Shih-Ming CHANG

Brief explanation

The abstract describes a method for manufacturing a semiconductor device. It involves the following steps: 

1. A conductive pattern is created on a dielectric layer's surface. 2. A mask pattern is formed over the dielectric layer, with an opening that aligns with the conductive pattern. 3. A portion of the conductive pattern is transformed into a high-resistant part that has a higher resistivity than the original conductive pattern. This transformation occurs only within the opening of the mask pattern. 4. Finally, the mask pattern is removed from the dielectric layer.

Abstract

In a method of manufacturing a semiconductor device, a conductive pattern is formed in a surface region of a dielectric layer, a mask pattern including an opening over the conductive pattern is formed over the dielectric layer, a part of the conductive pattern is converted into a high-resistant part having a higher resistivity than the conductive pattern before the converting through the opening, and the mask pattern is removed.

METHOD FOR DICING A SEMICONDUCTOR WAFER STRUCTURE (17709696)

Inventor Shu-Hui Su

Brief explanation

The abstract describes a method for creating an integrated chip. The method involves making three cuts in a semiconductor substrate. The first cut is made from one side of the substrate, the second cut is made from the opposite side, and the third cut is made separately from the second cut. This method allows for the formation of an integrated chip.

Abstract

The present disclosure relates to a method for forming an integrated chip. The method includes performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate. The method includes performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side. The method includes performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17709766)

Inventor Pei Ying LAI

Brief explanation

The abstract describes a method for creating a semiconductor structure. It involves forming two fin structures on a substrate, each with its own gate dielectric layer. A barrier layer is then applied over one of the gate dielectric layers, and the substrate is treated with a fluorine-containing gas. Afterward, a work function layer is formed over the other gate dielectric layer, and the substrate is treated with a different fluorine-containing gas.

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a first fin structure over a first region of a substrate and forming a second fin structure over a second region of a substrate, forming a first gate dielectric layer around the first fin structure and forming a second gate dielectric layer around the second fin structure, forming a barrier layer over the first gate dielectric layer, treating the substrate with a first fluorine-containing gas, forming a work function layer over the second gate dielectric layer after treating the substrate with the first fluorine-containing gas, and treating the substrate with a second fluorine-containing gas after forming the work function layer over the second gate dielectric layer.

PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME (17710815)

Inventor Tzu-Hsuan CHANG

Brief explanation

The abstract describes a method for creating a package structure. The process involves mixing cellulose nanofibrils and a two-dimensional material in a solvent to create a solution. The solvent is then removed to form a composite filler. This filler is mixed with a prepolymeric material to create a composite material. Finally, a molding process is used to shape the composite material into the desired package structure.

Abstract

A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a two-dimensional (2D) material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.

TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING (18331249)

Inventor Sheng-Chan Li

Brief explanation

The abstract describes an integrated chip structure that consists of a substrate and an interconnect structure. The interconnect structure contains multiple interconnects within a dielectric structure. A dielectric protection layer is present on the sidewall of the interconnect structure and also on the sidewall and recessed surface of the substrate. The bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.

Abstract

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.

SEMICONDUCTOR PACKAGES (17711060)

Inventor Yi-Jung Chen

Brief explanation

The abstract describes a semiconductor package that consists of a first integrated circuit and two types of vias: first through vias and fin-shaped through vias. The first through vias are arranged around the first integrated circuit, while the fin-shaped through vias are connected to the first through vias. The first through vias are positioned between the first integrated circuit and the fin-shaped through vias.

Abstract

A semiconductor package includes a first integrated circuit, a plurality of first through vias and a plurality of fin-shaped through vias. The first through vias surround the first integrated circuit. The fin-shaped through vias are physically connected to the first through vias respectively, wherein the first through vias are disposed between the first integrated circuit and the fin-shaped through vias.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF (17709470)

Inventor Kai-Ming Chiang

Brief explanation

The abstract describes a package structure that consists of several components. It includes a first redistribution circuit structure, which has a dielectric structure and a routing structure inside it. The dielectric structure has a trench that exposes the routing structure. There is also a semiconductor die that is placed on and connected to the first redistribution circuit structure. A connecting film is present in the trench, between the semiconductor die and the first redistribution circuit structure. The connecting film helps in thermal coupling between the semiconductor die and the routing structure. Additionally, there is a second redistribution circuit structure that is connected to the semiconductor die. This second redistribution circuit structure is also connected to the first redistribution circuit structure. The semiconductor die is positioned between the first redistribution circuit structure and the second redistribution circuit structure.

Abstract

A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film. The second redistribution circuit structure is disposed on and electrically coupled to the semiconductor die, the second redistribution circuit structure is electrically coupled to the first redistribution circuit structure, and the semiconductor die is disposed between the first redistribution circuit structure and the second redistribution circuit structure.

HIGH VOLTAGE PASSIVE DEVICE STRUCTURE (17708998)

Inventor Yuan-Yang Hsiao

Brief explanation

The abstract describes a device structure that includes a metal-insulator-metal (MIM) stack. The MIM stack consists of several layers, including conductor plate layers and insulator layers. The device structure also includes a ground via and a high voltage via, which are electrically coupled to specific plates in the conductor plate layers. The ground plate and high voltage plate overlap vertically, and the insulator layer between them is different from the insulator layer between other layers in the MIM stack.

Abstract

A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack. The MIM stack includes at least one lower conductor plate layer, a first insulator layer disposed over the at least one lower conductor plate layer, a first conductor plate layer disposed over the first insulator layer, a second insulator layer disposed over the first conductor plate layer, and a second conductor plate layer disposed over the second insulator layer. The device structure further includes a ground via extending through and electrically coupled to a first ground plate in the first conductor plate layer and a first via extending through and electrically coupled to a high voltage plate in the second conductor plate layer. The first ground plate vertically overlaps the high voltage plate and the second insulator layer is different from the first insulator layer.

SEMICONDUCTOR MEMORY DEVICE HAVING WORD LINES SURROUNDED BY MEMORY LAYERS AND METHOD OF MAKING THE SEMICONDUCTOR MEMORY DEVICE (17708199)

Inventor Meng-Han LIN

Brief explanation

The abstract describes a semiconductor memory device that consists of two memory units. Each memory unit has separate source/bit line portions, a word line, a memory film, and a channel region. The memory units are stacked on top of each other, and staircase vias penetrate the memory films to connect to the word lines.

Abstract

A semiconductor memory device includes first and second memory units, and first and second staircase vias. The first memory unit includes two first source/bit line portions separated from each other, a first word line surrounding the first source/bit line portions, a first memory film surrounding the first word line, and a first channel region between the first memory film and the first source/bit line portions. The second memory unit is disposed over the first memory unit, and includes two second source/bit line portions separated from each other, a second word line surrounding the second source/bit line portions, a second memory film surrounding the second word line, and a second channel region between the second memory film and the second source/bit line portions. The first and second staircase vias respectively penetrate the first and second memory films, and are respectively and electrically connected to the first and second word lines.

DC AND AC MAGNETIC FIELD PROTECTION FOR MRAM DEVICE USING MAGNETIC-FIELD-SHIELDING STRUCTURE (18332047)

Inventor Harry-Hak-Lay Chuang

Brief explanation

The abstract describes an integrated chip that consists of a semiconductor device and a shielding structure. The shielding structure is positioned next to the chip and is made up of multiple layers, including a dielectric layer and multiple metal layers. The purpose of this structure is to provide protection and shielding for the chip.

Abstract

In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.

PASSIVE DEVICE STRUCTURE STRESS REDUCTION (17711740)

Inventor Yuan-Yang Hsiao

Brief explanation

The abstract describes a method for creating a passive device structure in the back-end-of-line (BEOL) process. The method involves depositing multiple layers of conductive and insulating materials onto a substrate and then patterning these layers to form a specific pattern. One key step in the process is removing a right-angle edge from the first conductor layer.

Abstract

Methods for forming a back-end-of-line (BEOL) passive device structure are provided. A method according to the present disclosure includes depositing a first conductor layer over a substrate, patterning the first conductor layer to form a patterned first conductor layer, depositing a first insulation layer over the patterned first conductor layer, depositing a second conductor layer over the first insulation layer, patterning the second conductor layer to form a patterned second conductor layer, depositing a second insulation layer over the patterned second conductor layer, depositing a third conductor layer over the second insulation layer, and patterning the third conductor layer to form a patterned third conductor layer. The patterning of the first conductor layer includes removing a right-angle edge of the first conductor layer.

SEMICONDUCTOR DEVICE HAVING FUNCTIONAL PATTERNS IN REDUNDANT REGIONS OF DOUBLE SEAL RING (17711847)

Inventor Shan-Yu Huang

Brief explanation

The abstract describes a semiconductor structure that consists of different circuit regions and seal rings. The structure includes an inner seal ring that partially surrounds a circuit region, and an outer seal ring that partially surrounds the inner seal ring. The outer seal ring has a triangular corner seal ring structure at one corner. The inner seal ring has a corner adjacent to and spaced away from the triangular structure. The structure also includes a region between two sides of the corners that is parallel to one side of the outer seal ring. Additionally, there are multiple functional patterns within this region.

Abstract

A semiconductor structure includes a first circuit region; a first inner seal ring at least partially surrounding the first circuit region; and an outer seal ring at least partially surrounding the first inner seal ring. The outer seal ring includes a first corner and a substantially triangular corner seal ring (CSR) structure at the first corner. The first inner seal ring includes a second corner adjacent to and spaced away from the CSR structure. The semiconductor structure further includes a first region between a first side of the first corner and a first side of the second corner that is parallel to the first side of the first corner, and multiple functional patterns in the first region.

PACKAGE STRUCTURE WITH ANTENNA ELEMENT (18328915)

Inventor Yung-Ping CHIANG

Brief explanation

The abstract describes a package structure that consists of several components. These components include a dielectric structure, an antenna structure, a semiconductor device, a protective layer, and a conductive feature. The dielectric structure houses the other components, while the antenna structure is placed within the dielectric structure. The semiconductor device is positioned on top of the dielectric structure and is surrounded by a protective layer. The conductive feature serves to establish an electrical connection between the semiconductor device and the antenna structure. Additionally, a part of the antenna structure is located between the conductive feature and the dielectric structure.

Abstract

A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.

A METHOD (AND RELATED APPARATUS) FOR FORMING A SEMICONDUCTOR DEVICE WITH REDUCED SPACING BETWEEN NANOSTRUCTURE FIELD-EFFECT TRANSISTORS (18328117)

Inventor Zhi-Chang Lin

Brief explanation

The abstract describes a semiconductor device that includes a semiconductor fin projecting from a substrate. On top of the semiconductor fin, there are semiconductor nanostructures. A gate electrode surrounds the semiconductor fin and the nanostructures. A dielectric fin is placed over the substrate, and a dielectric structure is placed over the dielectric fin. The upper surface of the dielectric structure is positioned over the upper surface of the gate electrode. Additionally, a dielectric layer is placed over the substrate, with the dielectric fin separating the gate electrode and the nanostructures from the dielectric layer. The upper surface of the dielectric layer is positioned over the upper surface of the gate electrode and the dielectric structure, while the lower surface of the dielectric layer is positioned below the upper surface of the dielectric fin.

Abstract

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Methods Of Forming Optical Modules (17899863)

Inventor Jung-Huei Peng

Brief explanation

The abstract describes a method for forming optical modules. It involves creating multiple optical elements on separate wafers and aligning them together. The first and second wafers are aligned so that each first optical element overlaps with a corresponding second optical element. The first and second wafers are then bonded together to form a structure. The second and third wafers are also aligned so that each second optical element overlaps with a corresponding third optical element.

Abstract

Optical modules and methods of forming the same are provided. In an embodiment, an exemplary method includes forming multiple first optical elements over a first wafer, forming multiple second optical elements over a second wafer, forming multiple third optical elements over a third wafer, aligning the first wafer with the second wafer such that, upon the aligning of the first wafer with the second wafer, each first optical element is vertically overlapped with a corresponding second optical element. The method also includes bonding the first wafer with the second wafer to form a first bonded structure, aligning the second wafer with the third wafer such that, and upon bonding the second wafer of the first bonded structure to the third wafer, where upon the aligning of the second wafer with the third wafer, each second optical element is vertically overlapped with a corresponding third optical element.

ISOLATION STRUCTURE TO INCREASE IMAGE SENSOR PERFORMANCE (17828346)

Inventor Yen-Ting Chiang

Brief explanation

The abstract describes a type of image sensor that has multiple photodetectors placed in a substrate. The substrate has a front-side and a back-side surface. The image sensor also includes an outer isolation structure that surrounds the photodetectors and has a certain height. Additionally, there is an inner isolation structure located between the photodetectors, which has a smaller height compared to the outer isolation structure. Both the outer and inner isolation structures extend from the back-side surface towards the front-side surface of the substrate.

Abstract

Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The substrate comprises a front-side surface opposite a back-side surface. An outer isolation structure is disposed in the substrate and laterally surrounds the plurality of photodetectors. The outer isolation structure has a first height. An inner isolation structure is spaced between sidewalls of the outer isolation structure. The inner isolation structure is disposed between adjacent photodetectors in the plurality of photodetectors. The outer isolation structure and the inner isolation structure respectively extend from the back-side surface toward the front-side surface. The inner isolation structure comprises a second height less than the first height.

Structure and Method for Backside-Illuminated Image Device (17879536)

Inventor Hao-Lin Yang

Brief explanation

The abstract describes a structure for an image sensor, which is a device that captures and converts light into digital images. The structure includes a substrate, a photodetector, a gate electrode, a floating diffusion region, and an interconnect structure. The photodetector is located on the front side of the substrate and spans a certain dimension. The gate electrode partially overlaps the photodetector. The floating diffusion region is a doped region next to the photodetector. The interconnect structure is on the front surface of the substrate and includes two metal layers. The second metal layer has two metal features that are a certain distance apart along a certain direction. One of the metal features is connected to the doped feature. The ratio of the distance between the metal features to the dimension of the photodetector is greater than 0.3.

Abstract

An image sensor structure that further includes a first substrate having a front side and a back side; a photodetector disposed on the front side of the first substrate and spanning a dimension Dp along a first direction; a gate electrode formed on the front side of the first substrate and partially overlapping the photodetector; a doped region as a floating diffusion region formed on the front side of the first substrate and disposed next to the photodetector; and an interconnect structure disposed on the front surface of the first substrate and overlying the gate electrode. The interconnect structure includes a second metal layer over a first metal layer, the second metal layer further includes a first and second metal features distanced a distance Ds along the first direction, the first metal feature is electrically connected to the doped feature, and a first ratio Ds/Dp is greater than 0.3.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17709583)

Inventor Tsung-Lin LEE

Brief explanation

The abstract describes a method for creating a semiconductor structure. This method involves creating a fin structure with alternating layers of different semiconductors. The first semiconductor layers are then recessed to create notches, and passivation layers are added to the exposed sidewalls of these notches. Finally, inner spacer layers are formed within the notches.

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17711707)

Inventor Yan-Ting LIN

Brief explanation

The abstract describes a method for creating a structure on a substrate that involves forming multiple layers in a specific orientation. The layers are arranged in a certain direction and extend perpendicular to that direction. Silicon layers are grown on either side of each layer and then doped with boron. First silicon germanium layers are then grown on top of the silicon layers. Finally, a gate structure is formed around each layer.

Abstract

A method includes forming a plurality of channel layers above a (110)-orientated substrate, the channel layers arranged in a <110> direction normal to a top surface the (110)-orientated substrate and extending in a <10> direction perpendicular to the <110> direction; epitaxial growing a plurality of silicon layers on either side of each of the channel layers; doping the silicon layers with boron; epitaxial growing a plurality of first silicon germanium layers on the silicon layers; forming a gate structure surrounding each of the channel layers.

METHOD OF FORMING FULLY STRAINED CHANNELS (18329214)

Inventor Shahaji B. More

Brief explanation

The abstract describes a method for creating a structure in a semiconductor substrate. The method involves forming two wells, one for N-type material and one for P-type material. A layer of silicon is deposited over the wells, followed by a dielectric layer. A resist pattern is then formed over the dielectric layer, creating an opening above the N well. The dielectric and silicon layers are etched through the opening, leaving a portion of the silicon layer over the N well. The resist pattern is removed, and a second layer of silicon germanium (SiGe) is grown epitaxially over the remaining portion of the silicon layer. This growth process involves a baking step, followed by the deposition of a silicon seed layer and a SiGe layer, all performed at the same temperature.

Abstract

A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

GATE STRUCTURES FOR MULTI-GATE DEVICES (17750842)

Inventor Shih-Hang Chiu

Brief explanation

The abstract describes a method for fabricating a device on a substrate. The method involves removing a dummy gate stack from the substrate to create a gate trench, and then depositing various layers including a gate dielectric, work function layer, tungsten layer, and tungsten nitride layer.

Abstract

A method according to the present disclosure includes providing a substrate that includes a dummy gate stack wrapping over an active region, and a spacer layer extending along sidewalls of the dummy gate stack, selectively removing the dummy gate stack to form a gate trench exposing the active region, depositing a gate dielectric over the active region, depositing at least one work function layer over the gate dielectric layer, depositing a tungsten layer over the at least one work function layer, and depositing a tungsten nitride layer over the tungsten layer.

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (17700357)

Inventor Shih-Che LIN

Brief explanation

The abstract describes a semiconductor device structure and the methods used to create it. The structure includes several layers, such as a gate electrode layer, a source/drain epitaxial feature, a hard mask layer, and a contact etch stop layer. It also includes interlayer dielectric layers and treated portions of a second hard mask layer. The structure is designed to have coplanar top surfaces and includes an etch stop layer.

Abstract

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

HEAT SINK LAYOUT DESIGNS FOR ADVANCED FINFET INTEGRATED CIRCUITS (18322908)

Inventor Amit KUNDU

Brief explanation

This abstract describes a method of manufacturing a semiconductor device. The method involves creating an active device area in a substrate and then forming a first transistor within this area. The first transistor consists of a channel region, a source region, and a drain region. Additionally, a guard ring region is formed outside of the active device area. Within this guard ring region, a second transistor is created. The second transistor also has a channel region, source region, and drain region. However, the channel region of the second transistor is made from a semiconductor material with a higher thermal conductivity compared to the semiconductor material used in the first transistor's channel region.

Abstract

A method of making a semiconductor device includes forming an active device region in a substrate. The method further includes forming a first transistor in the active device region, the first transistor including a first channel region a first source region and a first drain region. The method further includes forming a guard ring region outside the active device region. The method further includes forming a second transistor in the guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF (17890571)

Inventor Chi-Ming HUANG

Brief explanation

The abstract describes a process for improving the uniformity and stability of etching rates during the fabrication of gate electrodes in semiconductor devices. By adjusting the shape of the sacrificial gate electrode, specifically making it more straight rather than bowl-shaped, the formation of voids in the replacement gate electrode can be reduced. This adjustment is achieved by performing a pullback etching process of the sidewall spacers before depositing the gate dielectric layer and work function metal layer, which creates a wider opening for filling the replacement gate electrode with metal.

Abstract

Some embodiments provide a process of tunning sidewall profiles of gate openings prior to filling a replacement gate electrode layer therein to improve etching rate uniformity and stability during a subsequent gate electrode etch back process. Particularly, the profile sacrificial gate electrode is adjusted to be more straight profile rather than a bowl type profile, which reduces the seam void created in the replacement gate electrode during the replacement gate process. In some embodiments, tuning the profile of gate opening further includes performing a pullback etching process of the sidewall spacers prior to depositing gate dielectric layer and work function metal layer to achieve a wider opening for metal gate filling in the replacement gate process.

SEMICONDUCTOR DEVICE STRUCTURE WITH FIN AND METHOD FOR FORMING THE SAME (17710499)

Inventor Zhiqiang WU

Brief explanation

The abstract describes a method for creating a semiconductor device structure. The method involves using a substrate, a fin, and a semiconductor layer. The fin is placed on top of the substrate, and the semiconductor layer is placed on top of the fin. The substrate and fin are made of different materials, as are the fin and semiconductor layer. A dielectric layer is then formed over the semiconductor layer and fin. A semiconductor structure is created on the side of the dielectric layer. A portion of the dielectric layer is removed from the top surface of the semiconductor layer. Finally, a gate is formed over the semiconductor layer, dielectric layer, and semiconductor structure.

Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a fin, and a semiconductor layer. The fin is over the substrate, the semiconductor layer is over the fin, the substrate and the fin are made of different materials, and the fin and the semiconductor layer are made of different materials. The method includes forming a dielectric layer over the semiconductor layer and the fin. The method includes forming a semiconductor structure over a sidewall of the dielectric layer. The method includes removing a first top portion of the dielectric layer over a top surface of the semiconductor layer. The method includes forming a gate over the semiconductor layer, the dielectric layer, and the semiconductor structure.

METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH LOCAL ISOLATION AND A SEMICONDUCTOR DEVICE WITH LOCAL ISOLATION (17710592)

Inventor Tsung-Lin LEE

Brief explanation

This abstract describes a method of manufacturing a semiconductor device. It involves creating a fin structure by stacking alternating layers of different semiconductors on a substrate. A sacrificial gate structure is then formed over the fin structure. The parts of the fin structure that are not covered by the sacrificial gate structure are etched to create a space for the source/drain region. An isolation region is formed at the bottom of this space. A source/drain epitaxial layer is then formed over the isolation region, creating a void region between the epitaxial layer and the substrate. This void region provides electrical isolation between the source/drain region and the substrate.

Abstract

In a method of manufacturing a semiconductor device a fin structure is formed in which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure that is not covered by the sacrificial gate structure is etched to form a source/drain space. An isolation region is formed at a bottom portion of the source/drain space. A source/drain epitaxial layer is formed over the isolation region in the source/drain space, and a void region in the isolation region is produced between the source/drain epitaxial layer and the substrate to cause electrical isolation between the source/drain region and the substrate.

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (17698696)

Inventor Shun-Siang JHAN

Brief explanation

This abstract describes a method for fabricating a semiconductor device. The method involves creating a layer of 2-D semiconductor material on a substrate. Source/drain contacts are then formed on specific regions of the semiconductor layer, and a gate structure is formed on the channel region. The formation of the source/drain contacts includes depositing a first metal layer on the semiconductor layer, followed by depositing a second metal layer with a higher melting point on top of the first metal layer.

Abstract

A method includes forming a 2-D semiconductor material layer over a substrate; forming source/drain contacts over source/drain regions of the 2-D semiconductor material layer; and forming a gate structure over a channel region of the 2-D semiconductor material layer. Forming the source/drain contacts includes performing a first deposition process to deposit a first metal layer over the 2-D semiconductor material layer; and after the first deposition process is completed, performing a second deposition process to deposit a second metal layer over the first metal layer, in which the second metal layer has a higher melting point than the first metal layer.

INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE (17812991)

Inventor Kuo-Chiang TSAI

Brief explanation

The abstract describes a method and device that involves a substrate with two transistor terminals. Contact structures are formed on each terminal, and then a via opening is created above the contacts. This opening is filled to create a non-linear via that connects the two contacts. The non-linear via has a shape that resembles waves or curves.

Abstract

A method and device according to the present disclosure includes a substrate that has a first transistor terminal such as a source feature and a second transistor terminal such as another source feature. Contact structures are formed on each source/drain feature. After forming the contact structures, a via opening is formed in dielectric materials above the contact structures, which is filled to form a non-linear via that extends from the contact on the first source feature to the contact on the second source feature. The non-linear via may include an outline in a top view of an undulating-shape having convex and/or concave portions.

ANALOG-TO-DIGITAL CONVERTING DEVICE AND METHOD OF OFFSET CALIBRATION (17817636)

Inventor Ting-Hao WANG

Brief explanation

This abstract describes an analog-to-digital converting device that consists of multiple stages of analog-to-digital converters (ADCs), calibration circuits, a data recovery circuit, and an output circuit. The first ADCs operate at a higher sampling frequency compared to the second ADC. They convert an input signal into quantized outputs. The calibration circuit adjusts the offsets of these quantized outputs and generates third and fourth quantized outputs. The data recovery circuit selects one of the third quantized outputs and subtracts it from the fourth quantized output to generate output data. The output circuit generates an output signal based on the third quantized outputs and the output data.

Abstract

An analog-to-digital converting device includes N-stage first analog-to-digital converters (ADCs), a second ADC, a first calibration circuit, a data recovery circuit and an output circuit. The N-stage first ADCs has a first sampling frequency that is (N+1)/N times of a second sampling frequency, and converts an input signal into first quantized outputs. The second ADC has the second sampling frequency, and converts the input signal into a second quantized output. The first calibration circuit calibrates offsets of the first quantized outputs and the second quantized output to generate third quantized outputs and a fourth quantized output. The data recovery circuit outputs, by the second sampling frequency, one of the third quantized outputs as a fifth quantized output, and subtracts the fifth quantized output from the fourth quantized output to generate output data. The output circuit generates an output signal according to the third quantized outputs and the output data.

LAMINATED STRUCTURE WITH PADS AND MANUFACTURING METHOD THEREOF (17709461)

Inventor Hao-Cheng Hou

Brief explanation

The abstract describes a laminated structure and its manufacturing methods. The structure includes an interconnect substrate with two surfaces, an insulating encapsulant wrapping the substrate, and a redistribution structure on the first surface. The redistribution structure has first and second pads, with protective patterns covering the first pads. The first pads have portions protruding from the fourth surface, and the protective patterns are in contact with the sidewalls and top surfaces of the pad portions.

Abstract

A laminated structure and the manufacturing methods thereof are provided. The structure includes an interconnect substrate having a first surface and a second surface opposite to the first surface, an insulating encapsulant laterally wrapping the interconnect substrate, and a redistribution structure disposed on the first surface of the interconnect substrate and electrically connected with the interconnect substrate. The redistribution structure has a third surface facing the first surface and a fourth surface opposite to the third surface. The redistribution structure includes first pads, second pads located beside the first pads, and protective patterns disposed on the first pads and covering the first pads. The first pads include pad portions protruded from the fourth surface and the protective patterns are in contact with sidewalls and top surfaces of the pad portions of the first pads.

CO-OPTIMIZATION OF MEMORY AND LOGIC DEVICES BY SOURCE/DRAIN MODULATION AND STRUCTURES THEREOF (17870341)

Inventor Ta-Chun Lin

Brief explanation

The abstract describes methods and structures for optimizing the use of memory and logic devices. It explains that a device consists of two regions, each containing a gate structure and a source/drain feature. The top surfaces of these features are level with each other, but the bottom surfaces are at different distances from the top surfaces. In some cases, the second distance is greater than the first distance.

Abstract

Methods and structures for the co-optimization of memory and logic devices. A device includes a substrate having a first region and a second region. The device may include a first gate structure disposed in the first region and a second gate structure disposed in the second region. The device may further include a first source/drain feature disposed adjacent to the first gate structure and a second source/drain feature disposed adjacent to the second gate structure. A first top surface of the first source/drain feature and a second top surface of the second source/drain feature are substantially level. A first bottom surface of the first source/drain feature is a first distance away from the first top surface, and a second bottom surface of the second source/drain feature is a second distance away from the second top surface. In some cases, the second distance is greater than the first distance.

MEMORY STRUCTURE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME (17707562)

Inventor Meng-Han LIN

Brief explanation

The abstract describes a semiconductor device that has a memory structure. The device includes a substrate, which is a base material, and the memory structure is placed on top of the substrate. The memory structure consists of several components. Firstly, there are two first conductive lines, which are thin wires that carry electrical signals. Between these lines, there is a channel element, which is a component that allows the flow of electrical current. The channel element has an air gap, which is a space filled with air. Additionally, there are two memory elements, each separating one of the first conductive lines from the channel element. These memory elements likely store and retrieve data. The abstract also mentions a method for manufacturing this semiconductor device, but it does not provide any details about the manufacturing process.

Abstract

A semiconductor device includes a substrate and a memory structure disposed over the substrate. The memory structure includes a pair of first conductive lines, a channel element disposed between the pair of the first conductive lines and formed with an air gap therein, a first memory element disposed to separate one of the pair of the first conductive lines from the channel element, and a second memory element disposed to separate the other one of the pair of the first conductive lines from the channel element. A method for manufacturing the semiconductor device is also disclosed.

SEAL METHOD TO INTEGRATE NON-VOLATILE MEMORY (NVM) INTO LOGIC OR BIPOLAR CMOS DMOS (BCD) TECHNOLOGY (18328080)

Inventor Cheng-Bo Shu

Brief explanation

The abstract describes a method to integrate non-volatile memory (NVM) devices with a logic or BCD (Bipolar-CMOS-DMOS) device. It involves forming an isolation structure in a semiconductor substrate to separate the memory region from the peripheral region. A doped well is created in the peripheral region, and a dielectric seal layer is applied to cover both regions. The seal layer is then removed from the memory region, and a memory cell structure is formed using a thermal oxidation process. The seal layer is also removed from the peripheral region, and a peripheral device structure with a gate electrode is formed.

Abstract

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

MEMORY WINDOW OF MFM MOSFET FOR SMALL CELL SIZE (18332080)

Inventor Hai-Dang Trinh

Brief explanation

The abstract describes an integrated chip that has multiple layers of interconnect dielectric material on top of a substrate. The chip includes a bottom electrode that extends through the dielectric layers and a top electrode. A ferroelectric layer is placed between the bottom and top electrodes, and it consists of a lower horizontal portion, an upper horizontal portion, and a sidewall portion that connects the lower and upper portions.

Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion.

TOP-ELECTRODE BARRIER LAYER FOR RRAM (18331228)

Inventor Hsing-Lien Lin

Brief explanation

The present application describes a type of memory cell called resistive random-access memory (RRAM). The RRAM cell includes a barrier layer on the top electrode, which prevents the movement of non-metal elements like nitrogen. This is important because if these non-metal elements reach the active metal layer of the RRAM cell, they can form a switching layer that increases the resistance of the cell. By blocking the movement of non-metal elements, the barrier layer helps to reduce this parasitic resistance in the RRAM cell.

Abstract

Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.