Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on November 30th, 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to the formation and structure of memory devices and semiconductor devices. These patents aim to improve the performance, functionality, and efficiency of these devices.

Summary: - TSMC has filed patents for methods of forming memory devices, semiconductor devices, and magnetic memory devices. - The methods involve the formation of specific layers, plugs, and structures to enhance the functionality and performance of the devices. - The patents also describe the use of magnetic materials, spin-orbit torque induction structures, and magnetic tunnel junction stacks to improve the operation of the devices. - TSMC's patents also include methods for etching magnetic tunneling junction structures and creating ultra-large height top electrodes for MRAM devices. - The organization has also filed patents for semiconductor structures with optical components and thermal control mechanisms. - Notable applications of these patents include data storage, magnetic sensors, and magnetoresistive random-access memory (MRAM) devices.

Bullet points:

• TSMC has filed patents for memory devices, semiconductor devices, and magnetic memory devices.
• The patents describe methods for forming specific layers, plugs, and structures to enhance device performance.
• Magnetic materials, spin-orbit torque induction structures, and magnetic tunnel junction stacks are used in the devices.
• Patents also cover methods for etching magnetic tunneling junction structures and creating large height top electrodes for MRAM devices.
• Semiconductor structures with optical components and thermal control mechanisms are also described.
• Applications include data storage, magnetic sensors, and MRAM devices.

Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023

PARTICLE REMOVER AND METHOD (18448963)

Main Inventor

Wen-Hao Cheng

TRANSDUCER DEVICE AND METHOD OF MANUFACTURE (17752558)

Main Inventor

Chi-Yuan Shih

Brief explanation

The patent application describes a method of creating a transducer, which is a device that converts one form of energy into another.

• The method involves depositing a layer of dielectric material on an electrode.
• The dielectric layer is then patterned to create protrusions of different sizes.
• The larger protrusions are called first protrusions, while the smaller ones are called second protrusions.
• The dielectric layer is then bonded to a second electrode using another layer of dielectric material.
• The sidewalls of the second dielectric layer create a cavity between the two electrodes.
• The first protrusions are located within this cavity.
• The purpose of this method is to create a transducer with specific features and characteristics.

Abstract

A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form first protrusions and second protrusions, where a first diameter of each of the first protrusions is larger than a second diameter of each of the second protrusions; and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the first protrusions are disposed in the cavity.

DEVICE FOR FORMING CONDUCTIVE POWDER (18447161)

Main Inventor

You-Hua CHOU

POLISHING METROLOGY (17898163)

Main Inventor

Chih Hung CHEN

CHEMICAL MECHANICAL POLISHING APPARATUS AND METHOD (18446842)

Main Inventor

Chun-Hsi Huang

Brief explanation

- The patent application describes an apparatus and method for detecting and adjusting the polishing process based on the profile of a polishing pad.

- The apparatus includes a polishing pad, a substrate carrier, and a detection module. - The detection module includes a probe and a beam, with the probe being able to measure the thickness of different areas on the polishing pad. - The probe can move along the beam to gather measurements from various locations on the polishing pad. - The detected profile of the polishing pad can be used to make adjustments to the polishing process, ensuring optimal polishing results. - This innovation aims to improve the efficiency and effectiveness of polishing processes by accurately detecting and adjusting for variations in the polishing pad profile.

Abstract

The present disclosure describes an apparatus and a method to detect a polishing pad profile during a polish process and adjust the polishing process based on the detected profile. The apparatus can include a polishing pad configured to polishing a substrate, a substrate carrier configured to hold the substrate against the polishing pad, and a detection module configured to detect a profile of the polishing pad. The detection module can include a probe configured to measure a thickness of one or more areas on the polishing pad, and a beam configured to support the probe, where the probe can be further configured to move along the beam.

SYSTEM AND METHOD FOR REMOVING DEBRIS DURING CHEMICAL MECHANICAL PLANARIZATION (18447211)

Main Inventor

Chun-Wei HSU

Brief explanation

- The patent application describes a chemical mechanical planarization system.

- The system includes a rotating chemical mechanical planarization pad. - A chemical mechanical planarization head places a semiconductor wafer in contact with the pad. - A slurry supply system supplies a slurry onto the pad during the process. - A pad conditioner is used to condition the pad during the process. - A suction system removes debris from the pad, including the pad conditioner and slurry.

Abstract

A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. A suction system removes pad conditioner debris and the slurry from the pad.

MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE (18364702)

Main Inventor

Kuei-Sung Chang

MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE (18446741)

Main Inventor

Chun-Wen Cheng

WIRE-BOND DAMPER FOR SHOCK ABSORPTION (18446740)

Main Inventor

Tsung-Lin Hsieh

DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE (17825225)

Main Inventor

Wen-Chuan Tai

SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL (18447543)

Main Inventor

Yi-Lin WANG

STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE (18446392)

Main Inventor

Ming-Yi SHEN

Brief explanation

The present disclosure is about exclusion rings used in processing semiconductor substrates in a processing chamber, specifically a chemical vapor deposition chamber.

• The exclusion ring has an alignment structure that works with an alignment structure on a platen where the exclusion ring will be placed during wafer processing.
• The first alignment structure has a guiding surface that helps position the second alignment structure within it.
• The exclusion rings described in the patent application improve the processing of semiconductor substrates in a chemical vapor deposition chamber.
• The alignment structures on the exclusion ring and platen ensure accurate positioning of the exclusion ring during wafer processing.
• The guiding surface on the first alignment structure aids in the reception and positioning of the second alignment structure.
• The patent application also includes methods for using these exclusion rings in semiconductor substrate processing.

Abstract

The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

DEPOSITION SYSTEM AND METHOD (18447911)

Main Inventor

Wen-Hao CHENG

Brief explanation

The patent application describes a deposition system that can clean itself by removing a deposited material from a collimator surface.

• The deposition system includes a substrate process chamber, a substrate pedestal, a target enclosure, a collimator, a vibration generating unit, and a cleaning gas outlet.
• The substrate pedestal supports a substrate, while the target enclosure surrounds the substrate process chamber.
• The collimator has hollow structures between the target and the substrate, which help control the deposition process.
• The vibration generating unit is used to generate vibrations that dislodge the deposited material from the collimator surface.
• The cleaning gas outlet is used to expel a cleaning gas that removes the dislodged material from the system.

Abstract

A deposition system is provided capable of cleaning itself by removing a target material deposited on a surface of a collimator. The deposition system in accordance with the present disclosure includes a substrate process chamber. The deposition includes a substrate pedestal in the substrate process chamber, the substrate pedestal configured to support a substrate, a target enclosing the substrate process chamber, and a collimator having a plurality of hollow structures disposed between the target and the substrate, a vibration generating unit, and cleaning gas outlet.

Apparatus and Method for Use with a Substrate Chamber (18447493)

Main Inventor

Li-Ting Wang

Brief explanation

The patent application describes an apparatus for monitoring and controlling the growth of a wafer in an epitaxial growth chamber. 

• The apparatus includes multiple pyrometers placed at different points on the front and backside of the wafer to monitor thermal radiation.
• A first controller adjusts the output of heating sources in different regions of the chamber based on the monitored thermal radiation from the backside of the wafer.
• A second controller adjusts the flow rate of precursors injected into the chamber based on the monitored thermal radiation from both the front and backside of the wafer.
• The apparatus allows for precise control of the growth process, ensuring optimal conditions for the wafer's epitaxial growth.

Abstract

In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.

APPARATUS FOR STORING AND TRANSPORTING SEMICONDUCTOR ELEMENTS, AND METHOD OF MAKING THE SAME (18231763)

Main Inventor

Tse-Lun HSU

Brief explanation

The patent application describes an apparatus with two parts that can be moved between an open and closed configuration. 

• The first part has a front and rear side wall, a top wall, and a pivotal pin structure.
• The pivotal pin structure has a base, shaft, and a head with a non-circular shape.
• The second part has a front and rear side wall, a bottom wall, and a pin holder.
• The pin holder has an opening that accepts the head of the pivotal pin structure.
• The first and second parts can be pivoted together to form a closed container.

Abstract

An apparatus includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pivotal pin structure extending from the first rear side wall. The at least one pivotal pin structure comprises a base, a shaft, and a head having a non-circular cross-sectional shape. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pin holder extending from the second rear side wall. The at least one pin holder defines an opening for accepting the head of the at least one pivotal pin structure at an alignment. The head of the at least one pivotal pin structure extends through the opening. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.

WAFER DRYING SYSTEM (18446858)

Main Inventor

Wei-Chun Hsu

Brief explanation

The patent application is for a system and method for drying wafers and detecting airborne molecular contaminants in the drying gas as a feedback parameter. 

• The system includes a wafer drying station that dispenses drying gas over one or more wafers to dry them.
• The system also includes a valve that diverts the drying gas into two portions.
• The first portion of the drying gas is exhausted through an exhaust line.
• The second portion of the drying gas is received by a detector, which determines a real-time property of the gas.
• A control unit then uses this real-time property to control the feedback operation of the wafer drying station.
• The purpose of this system is to ensure that the drying gas is free from contaminants that could potentially damage the wafers during the drying process.

Abstract

The present disclosure is directed to a wafer drying system and method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the system comprises a wafer drying station configured to dispense a drying gas over one or more wafers to dry the one or more wafers, a valve configured to divert the drying gas to a first portion and a second portion, and an exhaust line configured to exhaust the first portion of the drying gas. The system further comprises a detector configured to receive the second portion of the drying gas and to determine a real time property of the second portion of the drying gas, and a control unit configured to control a feedback operation of the wafer drying station based on the real time property of the second portion of the drying gas.

TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS (18150772)

Main Inventor

Jaw-Juinn HORNG

TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS (18170401)

Main Inventor

Szu-Lin Liu

CAPACITOR-BASED TEMPERATURE-SENSING DEVICE (18232329)

Main Inventor

Shih-Lien Linus LU

Brief explanation

The abstract describes a temperature-sensing device that can monitor temperature by using two capacitors with different oxide layer thicknesses. The device also includes a control logic circuit to determine if the temperature being monitored exceeds a threshold based on the breakdown of the oxide layers.

• Temperature-sensing device with a unique configuration for monitoring temperature.
• Includes two capacitors with different oxide layer thicknesses.
• Control logic circuit is used to determine if the monitored temperature exceeds a threshold.
• The breakdown of the oxide layers is used as an indicator of temperature exceeding the threshold.

Abstract

A temperature-sensing device configured to monitor a temperature is disclosed. The temperature-sensing device includes: a first capacitor comprising a first oxide layer with a first thickness; a second capacitor comprising a second oxide layer with a second thickness, wherein the second thickness of the second oxide layer is different from the first thickness of the first oxide layer; and a control logic circuit, coupled to the first and second capacitors, and configured to determine whether the monitored temperature is equal to or greater than a threshold temperature based on whether at least one of the first and second oxide layers breaks down.

ON-LINE ANALYSIS SYSTEM AND METHOD FOR SPECIALTY GASSES (17752730)

Main Inventor

Chiang Jeh CHEN

Brief explanation

- The patent application describes methods and systems for monitoring the quality of specialty fluids in real time.

- The specialty fluids are stored in gas cabinets and the monitoring is done using an analyzer and sampler. - The analyzer and sampler perform tests on the specialty fluids to determine their quality. - The data collected by the analyzer and sampler is stored and processed using an online data system. - The processed data is used to determine if the specialty fluids are suitable for use in workpiece processing tools. - The collected data is compared to manufacturer technical specifications to ensure the quality of the specialty fluids provided by the manufacturer.

Abstract

The present disclosure includes methods and systems for monitoring real time quality of specialty fluids within one or more specialty fluid containers stored within one or more gas cabinets. The methods and systems monitoring the real time quality of the specialty fluids may utilize an analyzer and sampler to perform one or more tests on the specialty fluids to determine the quality of the specialty fluids in real time. The data collected by the analyzer and sampler may be stored on and processed with the on-line data system to determine if the quality of the specialty fluids is sufficient to be introduced to one or more workpiece processing tools for processing one or more workpieces. The data collected may be compared to a manufacturer technical specification with respect to the specialty fluid to determine if the manufacturer is providing specialty fluids of sufficient quality.

IN-SITU APPARATUS FOR DETECTING ABNORMALITY IN PROCESS TUBE (18361777)

Main Inventor

Yu-Jen YANG

Brief explanation

The abstract describes a process tube device that can detect the presence of external materials in a fluid flowing through a tube. This device eliminates the need for a separate inspection device to check the surface of a wafer after applying fluid.

• The process tube device uses two methods to detect external materials.
• The first method involves using a light detecting sensor to directly measure the presence of external materials.
• The second method uses a sensor based on the principles of Doppler shift to indirectly measure the presence of external materials.
• Unlike the first method that relies on reflected or refracted light, the second method measures the velocity of the fluid flowing in the tube to detect the presence of external materials.
• This device allows for in-situ detection of external materials, making the inspection process more efficient and eliminating the need for additional equipment.

Abstract

A process tube device can detect the presence of any external materials that may reside within a fluid flowing in the tube. The process tube device detects the external materials in-situ which obviates the need for a separate inspection device to inspect the surface of a wafer after applying fluid on the surface of the wafer. The process tube device utilizes at least two methods of detecting the presence of external materials. The first is the direct measurement method in which a light detecting sensor is used. The second is the indirect measurement method in which a sensor utilizing the principles of Doppler shift is used. Here, contrary to the first method that at least partially used reflected or refracted light, the second method uses a Doppler shift sensor to detect the presence of the external material by measuring the velocity of the fluid flowing in the tube.

INTEGRATED BIOLOGICAL SENSING PLATFORM (18232318)

Main Inventor

Tsung-Tsun CHEN

Brief explanation

The patent application describes a device that can manipulate a liquid droplet using an electrode and assess its state using a sensing film and reference electrode. 

• The device includes an electrode that can change the contact angle of a liquid droplet when a voltage is applied to it.
• A sensing film is placed over the electrode to assess the state of the liquid droplet based on the voltage sensed at the electrode.
• A reference electrode is positioned above the electrode to provide a reference voltage.
• A microfluidic channel is present between the electrode and the reference electrode, allowing manipulation of the liquid droplet using the electrode.

Abstract

In an embodiment, a device includes: an electrode configured to change a contact angle of a liquid droplet above the electrode when a first voltage is applied to the electrode; a sensing film overlaying the electrode, wherein the electrode is configured for assessment of a state of the liquid droplet based on a second voltage sensed at the electrode; a reference electrode above the electrode, the reference electrode configured to provide a reference voltage; and a microfluidic channel between the electrode and the reference electrode, wherein the microfluidic channel is configured to manipulate the liquid droplet using the electrode.

On-Chip Heater (18232719)

Main Inventor

Tung-Tsun Chen

Brief explanation

The abstract describes a patent application for an on-chip heater design that improves temperature uniformity and reduces power consumption compared to existing designs. The heater is configured in concentric rings with non-uniform spacing between heating elements. This design is particularly suitable for integration with on-chip sensors that require precise temperature control.

• On-chip heater design patent application
• Concentric rings configuration with non-uniform spacing between heating elements
• Improved radial temperature uniformity compared to circular or square heating elements
• Lower power consumption
• Suitable for integration with on-chip sensors requiring tight temperature control

Abstract

An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.

STRUCTURE AND PROCESS FOR PHOTONIC PACKAGES (18366758)

Main Inventor

Chen-Hua Yu

Brief explanation

- The patent application describes semiconductor devices and methods for their formation.

- A method is described where a first material layer is placed between a second material layer and a semiconductor substrate. - A first waveguide is formed in the second material layer. - A photonic die is formed over the first waveguide. - A first cavity is formed in the semiconductor substrate, exposing the first layer. - The first cavity is filled with a first backfill material adjacent to the first layer. - An electronic die is electrically coupled to the photonic die. - Some methods include packaging the semiconductor device in a packaged assembly.

Abstract

Semiconductor devices and methods of forming the semiconductor devices are described herein. A method includes providing a first material layer between a second material layer and a semiconductor substrate and forming a first waveguide in the second material layer. The method also includes forming a photonic die over the first waveguide and forming a first cavity in the semiconductor substrate and exposing the first layer. Once formed, the first cavity is filled with a first backfill material adjacent the first layer. The methods also include electrically coupling an electronic die to the photonic die. Some methods include packaging the semiconductor device in a packaged assembly.

PACKAGED DEVICE WITH OPTICAL PATHWAY (18447560)

Main Inventor

Hsien-Wei Chen

Brief explanation

The patent application describes a packaged device that includes an optical integrated circuit (IC) with an optical feature. 

• The device also includes an interconnect structure with conductive features embedded in layers of dielectric materials that cover the optical feature.
• The interconnect structure is patterned to remove it from over the optical feature.
• A dielectric material with optically neutral properties is then formed over the optical feature.
• One or more electronic ICs can be bonded to the optical IC to create an integrated package.

Abstract

A packaged device includes an optical IC having an optical feature therein. An interconnect structure including layers of conductive features embedded within respective layers of dielectric materials overlie the optical feature. The interconnect structure is patterned to remove the interconnect structure from over the optical feature and a dielectric material having optically neutral properties, relative to a desired light wavelength(s) is formed over the optical feature. One or more electronic ICs may be bonded to the optical IC to form an integrated package.

METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE (18362983)

Main Inventor

Feng-Wei KUO

FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME (18448032)

Main Inventor

Chen-Hao HUANG

METHOD OF MAKING PHOTONIC DEVICE (18448046)

Main Inventor

Chien-Ying WU

METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING (18448095)

Main Inventor

Sui-Ying HSU

METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING (18358790)

Main Inventor

Yu-Hao CHEN

STRUCTURES AND PROCESS FLOW FOR INTEGRATED PHOTONIC-ELECTRIC IC PACKAGE BY USING POLYMER WAVEGUIDE (18232317)

Main Inventor

Yu-Hao CHEN

Brief explanation

- The patent application describes an apparatus and methods for a silicon photonic structure that integrates an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

- The structure also includes two or more polymer waveguides (PWGs) that are formed by layers of cladding polymer and core polymer. - An integration fan-out redistribution (InFO RDL) layer is placed on top of the PWGs. - The PWGs operate based on the refractive indexes of the cladding and core polymers. - Inter-layer optical signals coupling is achieved through edge-coupling, reflective prisms, and grating coupling. - The patent application also mentions a wafer-level system that implements the SiPh structure die and provides optical interconnections among the PWGs at the inter-die level.

Abstract

Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

Thermo-Electric Cooler for Dissipating Heat of Optical Engine (17896249)

Main Inventor

Hsing-Kuo Hsia

Brief explanation

The patent application describes a method for assembling a device that includes a photonic engine and a package component.

• The photonic engine is bonded onto an interposer, which is a substrate that provides electrical connections.
• The package component, which includes a device die, is then bonded onto the interposer.
• The package component and the photonic engine are encapsulated in a protective material.
• A thermal-electronic cooler is attached to the photonic engine to manage heat.
• A metal lid is attached to the package component for further protection.

Abstract

A method includes bonding a photonic engine onto an interposer, and bonding a package component onto the interposer. The package component includes a device die. The method further includes encapsulating the package component and the photonic engine in an encapsulant, attaching a thermal-electronic cooler to the photonic engine, and attaching a metal lid to the package component.

PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF (18232674)

Main Inventor

Yun-Yue LIN

EUV Lithography Mask With A Porous Reflective Multilayer Structure (18366136)

Main Inventor

Chih-Tsung Shih

Brief explanation

- The patent application describes a lithography mask that is used in the process of manufacturing electronic devices.

- The mask includes a substrate made of a low thermal expansion material (LTEM) to ensure stability during the manufacturing process. - The mask also includes a reflective structure, which is made up of multiple layers, including a first layer and a second layer. - The second layer of the reflective structure is porous, which allows for certain properties and characteristics to be achieved. - The mask is formed by creating a multilayer reflective structure over the LTEM substrate, using a series of film pairs consisting of a first layer and a porous second layer. - A capping layer is then added over the multilayer reflective structure to provide additional protection and stability. - Finally, an absorber layer is formed over the capping layer to complete the mask. - The innovation in this patent application lies in the use of a porous second layer in the reflective structure, which may offer unique advantages and benefits in the manufacturing process.

Abstract

A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). The lithography mask also includes a reflective structure disposed over the substrate. The reflective structure includes a first layer and a second layer disposed over the first layer. At least the second layer is porous. The mask is formed by forming a multilayer reflective structure over the LTEM substrate, including forming a plurality of repeating film pairs, where each film pair includes a first layer and a porous second layer. A capping layer is formed over the multilayer reflective structure. An absorber layer is formed over the capping layer.

PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME (18362046)

Main Inventor

Kuo-Hao LEE

SUB-RESOLUTION ASSIST FEATURES (18447425)

Main Inventor

Kenji Yamazoe

Brief explanation

- The patent application describes methods of fabricating semiconductor devices.

- The method involves receiving a design for a mask that will be used in the fabrication process. - The transmission cross coefficient (TCC) of an exposure tool is determined, which helps in understanding how the tool will affect the mask design. - The TCC is then broken down into different orders of eigenvalues and eigenfunctions, which are mathematical concepts used in analyzing the behavior of the TCC. - A kernel is calculated based on these eigenvalues and eigenfunctions. - The first sub-resolution assist feature (SRAF) seed map is determined by convoluting the mask design and the kernel. - The SRAF seed map is used to assist in the fabrication of the semiconductor device. - Overall, the patent application presents a method that utilizes mathematical analysis and convolution techniques to improve the fabrication process of semiconductor devices.

Abstract

Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.

PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE (18232264)

Main Inventor

An-Ren ZI

PHOTORESIST MATERIALS AND ASSOCIATED METHODS (18447568)

Main Inventor

Ming-Hui WENG

PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18232225)

Main Inventor

An-Ren Zi

Polymer Layer in Semiconductor Device and Method of Manufacture (18446562)

Main Inventor

Sih-Hao Liao

Brief explanation

The patent application describes a method of manufacturing a semiconductor device using a polymer mixture.

• The method involves applying the polymer mixture onto a substrate.
• A portion of the polymer mixture is exposed and developed to form a dielectric layer.
• The developed dielectric layer is then cured to enhance its properties.
• The polymer mixture consists of a polymer precursor, a photosensitizer, and a solvent.
• The polymer precursor used in the mixture is a polyamic acid ester.

Abstract

A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232220)

Main Inventor

Yen-Hao CHEN

UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232774)

Main Inventor

Ming-Hui WENG

PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN (18232717)

Main Inventor

An-Ren ZI

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS (18365529)

Main Inventor

Wen-Zhan Zhou

APPARATUS, SYSTEM AND METHOD (18447104)

Main Inventor

Po-Han Wang

Brief explanation

The patent application describes an apparatus and method for effectively removing evaporated material.

• The apparatus includes a hot plate and an exhaust hood assembly suspended over the hot plate.
• The exhaust hood assembly consists of a trench plate, a cover plate, and a single exhaust pipe header.
• The exhaust hood assembly reduces condensation and collects any remaining condensation to prevent it from affecting further manufacturing steps.

Abstract

An apparatus and a method for effectively exhausting evaporated material are provided. In an embodiment the apparatus includes a hot plate and an exhaust hood assembly suspended over the hot plate. The exhaust hood assembly includes a trench plate, a cover plate over the trench plate and a single exhaust pipe header over and attached to a single exhaust opening of the cover plate. During operation, the exhaust hood assembly reduces the amount of condensation and also collects any remaining condensation in order to help prevent condensation from impacting further manufacturing steps.

PHOTORESIST WITH POLAR-ACID-LABILE-GROUP (18447441)

Main Inventor

An-Ren Zi

Brief explanation

- The patent application describes a method for making a semiconductor device.

- The method involves using a photoresist, which is a material that is sensitive to light. - The photoresist used in this method contains an acid-labile group (ALG) connected to a polar unit. - The method includes several steps: forming the photoresist over a substrate, exposing the photoresist to a radiation beam, baking the photoresist, and performing a developing process. - The purpose of the radiation beam exposure is to create a pattern on the photoresist. - Baking the photoresist helps to stabilize the pattern. - The developing process is used to remove the parts of the photoresist that were not exposed to the radiation beam, leaving behind the desired pattern. - This method can be used in the manufacturing of semiconductor devices.

Abstract

Methods and materials for making a semiconductor device are described. The method includes forming a photoresist over a substrate. The photoresist includes an acid-labile group (ALG) connected to a polar unit. The method also includes exposing the photoresist to a radiation beam, baking the photoresist and performing a developing process to the photoresist.

METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR (18358904)

Main Inventor

Hung-Jui Kuo

SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (18446870)

Main Inventor

Kai-Chieh CHANG

OPTIMIZED MASK STITCHING (18231070)

Main Inventor

Sagar TRIVEDI

OPTICAL PROXIMITY CORRECTION AND PHOTOMASKS (18361879)

Main Inventor

Dong-Yo Jheng

Brief explanation

The patent application describes a method for optimizing the fabrication of masks used in lithographic processes. 

• The method involves receiving a layout for the mask and determining target contours for different lithographic process conditions.
• A modification is made to the layout and then simulated under different process conditions to generate simulated contours.
• The cost of the modification is determined by comparing the simulated contours with the target contours.
• If the cost is within a predetermined threshold, the modification is provided for fabricating the mask.

Abstract

A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES (18232745)

Main Inventor

Yih-Chen SU

MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW (18447361)

Main Inventor

Chun-Kai CHANG

SEMICONDUCTOR WAFER COOLING (18362037)

Main Inventor

Yung-Yao LEE

MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME (18355222)

Main Inventor

Saman M. I. ADHAM

FAULT DIAGNOSTICS (18303219)

Main Inventor

Sandeep Kumar Goel

METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW (18447170)

Main Inventor

Chung-Pin CHOU

Brief explanation

- The patent application describes a system for detecting defects in semiconductor wafers.

- The system captures test images of the semiconductor wafer. - These test images are then analyzed using a machine learning process. - An analysis model, trained with the machine learning process, generates simulated integrated circuit layouts based on the test images. - The system compares these simulated layouts to reference integrated circuit layouts to detect defects in the semiconductor wafer.

Abstract

A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17821559)

Main Inventor

Johnny Chiahao LI

METHOD FOR CHIP INTEGRATION (17828648)

Main Inventor

Yung Feng Chang

SEMICONDUCTOR DEVICE (18361815)

Main Inventor

Yu-Jen CHEN

ANTI-FUSE ARRAY (18446684)

Main Inventor

Meng-Sheng CHANG

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME (18446771)

Main Inventor

Yu-Jung CHANG

METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS (18447964)

Main Inventor

Yen-Pin CHEN

SILICON PHOTONICS SYSTEM (18155980)

Main Inventor

Feng-Wei KUO

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (18354377)

Main Inventor

John LIN

TRANSMISSION GATE STRUCTURE (18362195)

Main Inventor

Shao-Lun CHIEN

DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS (18446745)

Main Inventor

Yi-Lin CHUANG

Brief explanation

- This patent application describes a system and method for predicting design rule check (DRC) violations in a placement layout before routing is performed.

- The system includes DRC violation prediction circuitry that receives placement data associated with the layout. - The circuitry inspects the placement data, which may include data for different regions of the layout. - The circuitry predicts whether there would be systematic DRC violations in the layout if it is routed. - The innovation aims to identify potential violations early in the design process, allowing for adjustments to be made before routing. - This can help save time and resources by avoiding the need to rework the layout after routing. - The system provides a more efficient and accurate way to predict DRC violations compared to traditional methods.

Abstract

Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS (18447455)

Main Inventor

Yi-Lin CHUANG

Brief explanation

- This patent application describes a system and method for predicting design rule check (DRC) violations in a placement layout before routing is performed.

- The system includes DRC violation prediction circuitry that receives placement data associated with the layout. - The circuitry inspects the placement data, which may include data for different regions of the layout. - The circuitry predicts whether there would be systematic DRC violations in the layout if it is routed. - The goal is to identify potential violations early in the design process to avoid costly rework later on.

Abstract

Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT (18448143)

Main Inventor

Fong-Yuan CHANG

METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK (18231769)

Main Inventor

Win-San KHWA

Brief explanation

The patent application describes a method and apparatus for improving the defect tolerability of a hardware-based neural network.

• The method involves performing calculations on the first neurons of a neural network's first layer.
• A first pattern of a memory cell array is received.
• A second pattern of the memory cell array is determined based on a third pattern.
• At least one pair of columns of the memory cell array is determined using the first pattern and the second pattern.
• Input data of two columns in each pair of columns of the memory cell array is switched.
• Output data of the two columns in each pair of columns of the memory cell array is switched to determine the values on the first neurons of the first layer.

Abstract

Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY (17824306)

Main Inventor

Chieh Lee

CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER (18232768)

Main Inventor

Ku-Feng LIN

Brief explanation

The patent application describes circuits and methods for compensating mismatches in sense amplifiers.

• The circuit includes a first branch and a second branch.
• The first branch consists of a first transistor, a second transistor, and a first node.
• The second branch consists of a third transistor, a fourth transistor, and a second node.
• The first node is connected to the gates of the third and fourth transistors.
• The second node is connected to the gates of the first and second transistors.
• A first plurality of trimming transistors is connected in parallel to the second transistor.
• A second plurality of trimming transistors is connected in parallel to the fourth transistor.

Abstract

Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

MEMORY DEVICE WITH SOURCE LINE CONTROL (18232542)

Main Inventor

Perng-Fei Yuh

Systems and Methods for Controlling Power Management Operations in a Memory Device (18446818)

Main Inventor

Sanjeev Kumar Jain

ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES (18446072)

Main Inventor

Chien-Yuan Chen

FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR (17826180)

Main Inventor

Elia Ambrosi

MEMORY DEVICE WITH REDUCED AREA (17752662)

Main Inventor

Chun-Ying Lee

THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY (18232539)

Main Inventor

Meng-Sheng Chang

NON-VOLATILE MEMORY CIRCUIT AND METHOD (18448152)

Main Inventor

Gu-Huan LI

REPELLENT ELECTRODE FOR ELECTRON REPELLING (18448026)

Main Inventor

Ching-Heng YEN

Brief explanation

- The patent application is about a repellent electrode used in an ion implanter.

- The repellent electrode has a shaft and a repellent body with a repellent surface. - The surface shape of the repellent surface matches the shape of the inner chamber space of the source arc chamber. - The gap between the edge of the repellent body and the inner sidewall of the source arc chamber is minimized to avoid a short circuit. - The purpose of the invention is to prevent a short circuit between the conductive repellent body and the conductive inner sidewall of the source arc chamber.

Abstract

The current disclosure is directed to a repellent electrode used in a source arc chamber of an ion implanter. The repellent electrode includes a shaft and a repellent body having a repellent surface. The repellent surface has a surface shape that substantially fits the shape of the inner chamber space of the source arc chamber where the repellent body is positioned. A gap between the edge of the repellent body and the inner sidewall of the source arc chamber is minimized to a threshold level that is maintained to avoid a short between the conductive repellent body and the conductive inner sidewall of the source arc chamber.

ATOM PROBE TOMOGRAPHY SPECIMEN PREPARATION (18448014)

Main Inventor

Shih-Wei HUNG

Brief explanation

The patent application describes a method for preparing an atom probe tomography (APT) specimen on a wafer.

• APT specimen is formed directly on a specific region of the wafer called DUT (Device Under Test).
• A laser is used to create a trench in the DUT and bump structures within the trench.
• The laser patterning creates a coarse surface texture on the bump structures.
• A low-kV gas ion milling process is then used to shape the bump structures into the APT specimen.
• The APT specimen is integrated with the substrate or support structure beneath it.
• The method utilizes a dual-beam focused ion beam (FIB) microscope for the ion milling process.

Abstract

The disclosure is directed to techniques in preparing an atom probe tomography (“APT”) specimen. The disclosed techniques form an APT specimen or sample directly on a DUT region on a wafer. The APT specimen is formed integrally to the substrate or the support structure, e.g., a carrier, under the APT specimen. A laser patterning is conducted to form a trench in the DUT and one or more bump structures in the trench. The laser patterning is relatively coarse and forms a coarse surface texture on each of the bump structures. A low-kV gas ion milling using a dual-beam focused ion beam (“FIB”) microscopes is then conducted to shape the bump structures into APT specimen.

FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL (18447410)

Main Inventor

Sheng-Chieh HUANG

DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING (18231165)

Main Inventor

Ming Che CHEN

SYSTEM AND METHOD FOR PARTICLE CONTROL IN MRAM PROCESSING (18231740)

Main Inventor

Tsung-Han Kuo

Brief explanation

- The patent application describes a system and method for reducing particle contamination on substrates during a deposition process.

- The system includes a processing chamber that can be sealed to create a pressurized environment, and it contains a plasma, a target, and a substrate. - A particle control unit is also included in the system, which is designed to provide an external force to charged atoms and contamination particles in the plasma. - The charged atoms and contamination particles are generated by the target when it comes into direct contact with the plasma. - The external force exerted by the particle control unit is intended to direct the charged atoms towards the top surface of the substrate, while directing the contamination particles away from the top surface of the substrate. - The purpose of this system and method is to minimize particle contamination on the substrate during the deposition process, which can improve the quality and reliability of the deposited film.

Abstract

A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.

SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS (18361767)

Main Inventor

Yen-Liang CHEN

Brief explanation

The patent application describes a system and method for detecting the condition of a processing chamber used in semiconductor manufacturing.

• The system includes a step where a wafer-less processing is performed in the chamber to assess the condition of the chamber walls.
• By analyzing the residual gas produced during the wafer-less processing, an operator or process controller can determine if the chamber walls need to be cleaned.
• This method allows for proactive maintenance of the processing chamber, ensuring optimal performance and preventing potential issues caused by deteriorated chamber walls.

Abstract

The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.

SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS (18361771)

Main Inventor

Yen-Liang CHEN

Brief explanation

- The patent application describes a system and method for detecting the condition of a processing chamber.

- The method involves performing a wafer-less processing step in the chamber to assess the condition of the chamber walls. - By analyzing the residual gas produced during the wafer-less processing step, an operator or process controller can determine if the chamber walls need to be cleaned. - This approach allows for proactive maintenance of the processing chamber, potentially reducing downtime and improving overall efficiency.

Abstract

The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.

SEMICONDUCTOR TOOL FOR COPPER DEPOSITION (18447557)

Main Inventor

Chia-Hung TSAI

METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS (18225576)

Main Inventor

Wei-Lin CHANG

INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES (18359552)

Main Inventor

Po-Chuan Wang

Brief explanation

This patent application describes a method of forming a semiconductor device. Here are the key points:

• The method starts by forming a first conductive feature in a dielectric layer over a substrate.
• A second dielectric layer is then formed over the first dielectric layer.
• The second dielectric layer is etched using a patterned mask layer to create an opening that exposes the first conductive feature.
• After the etching, an ashing process is performed to remove the patterned mask layer.
• The opening is then wet cleaned, which enlarges the bottom portion of the opening.
• Finally, the opening is filled with a first electrically conductive material.

Overall, this method provides a way to create a semiconductor device with precise openings and improved conductivity.

Abstract

A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

SEMICONDUCTOR DEVICE PRE-CLEANING (17804447)

Main Inventor

Yi-Hsiang CHAO

APPARATUS FOR ELECTRO-CHEMICAL PLATING (18231196)

Main Inventor

Kuo-Lung HOU

Forming Low-Stress Silicon Nitride Layer Through Hydrogen Treatment (18358508)

Main Inventor

Wei-Che Hsieh

Brief explanation

- The patent application describes a method for depositing a silicon nitride layer on a wafer.

- The method involves placing the wafer into a process chamber. - A silicon-containing precursor is introduced into the process chamber. - The silicon-containing precursor is then purged from the process chamber. - Hydrogen radicals are introduced into the process chamber. - The hydrogen radicals are then purged from the process chamber. - A nitrogen-containing precursor is introduced into the process chamber. - The nitrogen-containing precursor is then purged from the process chamber.

• The method provides a way to deposit a silicon nitride layer on a wafer.
• It involves a series of steps including introducing and purging different precursors and radicals.
• The method can be used in semiconductor manufacturing processes.
• It may improve the quality and performance of the silicon nitride layer.
• The method may offer advantages in terms of efficiency and reliability.

Abstract

A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18446953)

Main Inventor

Chun-Yen Peng

Brief explanation

- The patent application describes a method for forming a crystalline high-k dielectric layer and controlling its crystalline phase and orientation during an anneal process.

- The method involves using seeding sections of the dielectric layer as nucleation sites and a capping layer mask during the anneal process to control the crystal growth. - The location of the nucleation sites and the arrangement of the capping layer allow for precise control over the orientation and phase of the crystal growth. - By modifying the dopants and process controls, the phase of the dielectric layer can be adjusted to enhance its permittivity and/or ferroelectric property.

Abstract

A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

PRE-TREATMENT APPARATUS (18188929)

Main Inventor

Chun-Hsiang WANG

Brief explanation

- The patent application describes a pre-treatment apparatus that can be added to a wafer track system.

- The purpose of the pre-treatment is to reduce friction at the edges of a substrate. - This reduction in edge friction helps prevent the formation of back side edge particles during subsequent processing operations. - The pre-treatment apparatus can deliver one or more gases to treat the top and/or bottom surfaces of the substrate. - It can also treat the back side edges of the substrate to further reduce edge friction and prevent overlay defects.

Abstract

A pre-treatment apparatus can be added as a module of a wafer track system, where the pre-treatment is designed to reduce friction at the edges of a substrate. Reducing edge friction can help prevent back side edge particles during attachment to a vacuum chuck in a subsequent processing operation that can occur, for example, in an exposure device. The pre-treatment apparatus can be configured to deliver one or more gases to treat top and/or bottom surfaces of a substrate. The pre-treatment apparatus can treat back side edges of a substrate to reduce edge friction of the substrate and to prevent overlay defects.

DEVICE AND METHOD FOR HIGH PRESSURE ANNEAL (18365517)

Main Inventor

Szu-Ying Chen

Brief explanation

- The patent application describes methods and devices for performing a high pressure anneal process during the formation of a semiconductor device.

- The high pressure anneal process can be either a dry process with process gases or a wet process with steam. - The purpose of the high pressure anneal process is to enhance the formation of the semiconductor device. - The invention provides embodiments of devices that can create and maintain the required pressurized environment for the anneal process. - The patent application emphasizes the importance of the high pressure anneal process in improving the performance and reliability of semiconductor devices.

Abstract

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

SYSTEM AND METHOD FOR MULTIPLE STEP DIRECTIONAL PATTERNING (18447869)

Main Inventor

Chih-Kai YANG

Brief explanation

The abstract of the patent application describes a semiconductor process system that uses an ion source to bombard a photoresist structure on a wafer. The system reduces the width of the photoresist structure by subjecting it to multiple distinct ion bombardment steps with different characteristics.

• The semiconductor process system uses an ion source to bombard a photoresist structure on a wafer.
• The purpose of the bombardment is to reduce the width of the photoresist structure.
• The system achieves this by subjecting the photoresist structure to multiple distinct ion bombardment steps.
• Each ion bombardment step has different characteristics, which contribute to the reduction of the photoresist structure width.
• The system employs a specific process to control and optimize the ion bombardment steps.
• The innovation lies in the use of multiple distinct ion bombardment steps with different characteristics to achieve a more precise reduction in the width of the photoresist structure.

Abstract

A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (17829154)

Main Inventor

Po-Han LIN

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (18232758)

Main Inventor

Chun-Wei LIAO

EUV PHOTOMASK AND RELATED METHODS (18366397)

Main Inventor

Chi-Hung LIAO

Brief explanation

The patent application describes a method of fabricating a semiconductor device using a resist layer and an exposure process.

• The method involves providing a first substrate and applying a resist layer on top of it.
• An exposure process is then performed on the resist layer using a radiation source and an intervening mask.
• The intervening mask consists of a second substrate, a multi-layer structure, a capping layer, and an absorber layer.
• The absorber layer has a main pattern area and an opening area that is located at a distance from the main pattern area.
• After the exposure process, the resist layer is developed to create a patterned resist layer.

Abstract

A method of fabricating a semiconductor device includes providing a first substrate and forming a resist layer over the first substrate. In some embodiments, the method further includes performing an exposure process to the resist layer. The exposure process includes exposing the resist layer to a radiation source through an intervening mask. In some examples, the intervening mask includes a second substrate, a multi-layer structure formed over the second substrate, a capping layer formed over the multi-layer structure, and an absorber layer disposed over the capping layer. In some embodiments, the absorber layer includes a first main pattern area and an opening area spaced a distance from the first main pattern area. In various examples, the method further includes, after performing the exposure process, developing the exposed resist layer to form a patterned resist layer.

Method of Forming a Semiconductor Device by Driving Hydrogen into a Dielectric Layer from Another Dielectric Layer (18358609)

Main Inventor

Hongfa Luan

Brief explanation

The patent application describes a thermal treatment process that can be used after a high-pressure anneal process in a field effect transistor.

• The thermal treatment process helps to keep hydrogen at the interface between a channel region and a gate dielectric layer.
• It also removes hydrogen from the bulk portion of the gate dielectric layer.
• This process can reduce the amount of threshold voltage shift caused by a high-pressure anneal.
• The high-pressure anneal and thermal treatment process can be performed at any time after the gate dielectric layer is formed.
• This process does not disrupt the existing process flow.

Abstract

Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

SURFACE OXIDATION CONTROL OF METAL GATES USING CAPPING LAYER (18230712)

Main Inventor

Pei-Yu Chou

Brief explanation

The patent application describes a method for fabricating a semiconductor device with a replacement gate stack. Here are the key points:

• A dummy gate stack is formed on a semiconductor fin.
• Gate spacers are formed on the sidewalls of the dummy gate stack.
• A first inter-layer dielectric is formed, with the gate spacers and dummy gate stack inside it.
• The dummy gate stack is removed, creating a trench between the gate spacers.
• A replacement gate stack is formed in the trench.
• A dielectric capping layer is deposited, with its bottom surface contacting the top surface of the replacement gate stack and the first inter-layer dielectric.
• A second inter-layer dielectric is deposited over the dielectric capping layer.
• A source/drain contact plug is formed, extending into the second inter-layer dielectric, dielectric capping layer, and first inter-layer dielectric.

Abstract

A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

AMBIENT CONTROLLED TWO-STEP THERMAL TREATMENT FOR SPIN-ON COATING LAYER PLANARIZATION (18446416)

Main Inventor

Chen-Fong TSAI

Brief explanation

The patent application describes a method to reduce thickness variation in a spin-on coating layer applied over trenches in a photoresist stack.

• The method involves a two-step thermal treatment process for the spin-on coating layer.
• In the first step, the spin-on coating layer is heated at a temperature below its cross-linking temperature, causing it to flow and spread evenly.
• In the second step, the spin-on coating layer is heated at a second temperature, which triggers cross-linking and stabilizes the layer.
• This process helps to minimize thickness variations in the spin-on coating layer, even when applied over trenches with different pattern densities.

Abstract

To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

Plasma-Assisted Etching Of Metal Oxides (18447943)

Main Inventor

Chansyun David YANG

Brief explanation

- The patent application describes methods and systems for using plasma to etch a metal oxide.

- The method involves modifying the surface of the metal oxide using a first gas. - A top portion of the metal oxide is then removed through a ligand exchange reaction. - Finally, the surface of the metal oxide is cleaned using a second gas.

Abstract

The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.

METHODS FOR FORMING POLYCRYSTALLINE CHANNEL ON DIELECTRIC FILMS WITH CONTROLLED GRAIN BOUNDARIES (18446415)

Main Inventor

Cheng-Hsien WU

Brief explanation

The abstract describes a method for forming a polycrystalline semiconductor layer in a patent application. Here is a simplified explanation of the abstract:

• The method involves several steps to form a polycrystalline semiconductor layer.
• First, a dielectric layer is formed, and a plurality of spacers are placed over it.
• The dielectric layer is then etched using the spacers as a mask, creating a recess in the dielectric layer.
• An amorphous semiconductor layer is deposited over the spacers and the dielectric layer, filling the recess.
• Finally, the amorphous semiconductor layer is recrystallized, resulting in the formation of a polycrystalline semiconductor layer.

Bullet points explaining the patent/innovation:

• The method provides a way to form a polycrystalline semiconductor layer, which can have improved electrical properties compared to amorphous or single-crystal semiconductor layers.
• By using spacers as an etch mask, the method allows for precise and controlled etching of the dielectric layer, ensuring accurate formation of the recess.
• The deposition of the amorphous semiconductor layer over the spacers and dielectric layer helps to fill the recess, ensuring a uniform and continuous polycrystalline semiconductor layer.
• The recrystallization process transforms the amorphous semiconductor layer into a polycrystalline structure, which can enhance the conductivity and performance of the semiconductor material.
• This method can be used in various semiconductor applications, such as integrated circuits, solar cells, and display technologies, to improve device performance and efficiency.

Abstract

A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.

METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL (18447810)

Main Inventor

Yun-Jui HE

NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL (18446652)

Main Inventor

Ya-Wen Chiu

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447389)

Main Inventor

Wei-Chih Chen

Brief explanation

- The patent application describes a passivation layer and conductive via that improve the transmittance of imaging energy within the passivation layer material.

- The increased transmittance allows for better control over the contours of openings formed in the passivation layer. - Once the openings are formed, conductive vias can be created within them. - The innovation aims to enhance the performance and functionality of passivation layers and conductive vias in electronic devices.

Abstract

A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447409)

Main Inventor

Wei-Yu Chen

Brief explanation

The patent application describes a method for forming solder connections in electronic devices. 

• The method involves applying solder paste to certain areas of a redistribution structure, which has a lower melting temperature.
• Solder bumps, with a higher melting temperature, are then formed on an interconnect structure.
• The solder bumps are placed on the regions of solder paste.
• A first reflow process is performed at a lower temperature, causing the solder paste to melt and form connections.
• After the first reflow process, a second reflow process is performed at a higher temperature to further strengthen the connections.

Abstract

A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING (18447443)

Main Inventor

Po-Chen Lai

Brief explanation

The patent application describes a method for manufacturing semiconductor devices.

• A first redistribution structure is created.
• Semiconductor devices are bonded to the first redistribution structure.
• The semiconductor devices are then encapsulated in an encapsulant.
• Openings are formed within the encapsulant, specifically along the corners, to reduce stress and prevent cracks.

Abstract

Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME (18447460)

Main Inventor

Hsien-Wei Chen

Brief explanation

The patent application describes a method for forming stacked semiconductor devices.

• Contact pads are formed on a die.
• A passivation layer is deposited over the contact pads.
• The passivation layer is patterned to expose the contact pads.
• A buffer layer is deposited over the passivation layer and contact pads.
• The buffer layer is patterned to expose a set of contact pads.
• First conductive pillars are formed in the exposed contact pads.
• Conductive lines are formed over the buffer layer and terminate with the first conductive pillars.
• An external connector structure is formed over the first conductive pillars and conductive lines.
• The first conductive pillars connect the contact pads to the external connector structure.

Abstract

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Semiconductor Package and Method of Forming Thereof (18447428)

Main Inventor

Jiun Yi Wu

Brief explanation

The patent application describes a method of forming a semiconductor device. 

• The method involves attaching a first local interconnect component to a first substrate using a first adhesive.
• A first redistribution structure is then formed over a first side of the first local interconnect component.
• The first local interconnect component and the first redistribution structure are removed from the first substrate and attached to a second substrate.
• The first adhesive is removed from the first local interconnect component.
• An interconnect structure is formed over a second side of the first local interconnect component and the first encapsulant, with a first conductive feature of the interconnect structure being physically and electrically coupled to a second conductive feature of the first local interconnect component.

Abstract

A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect co

CHEMICAL DISPENSING SYSTEM (18447353)

Main Inventor

Ming-Chieh HSU

UNDER BOAT SUPPORT WITH ELECTROSTATIC DISCHARGE STRUCTURE (18162538)

Main Inventor

Ying-Hao WANG

Brief explanation

The abstract describes an under boat support (UBS) that is designed to be electrostatic discharge (ESD) safe. It consists of a ceramic body and a conductive body, which are connected by an adhesive. 

• The UBS is made of an ESD safe ceramic body and a conductive body.
• The ceramic body and conductive body are joined together using a high-temperature resistant adhesive.
• The UBS includes a plurality of springs that are embedded within the adhesive.
• The springs extend from the conductive body to the ceramic body, forming electrical pathways.
• The springs ensure that the ceramic body is electrically coupled to the conductive body, providing ESD protection.

Abstract

An under boat support (UBS) includes an electrostatic discharge (ESD) safe ceramic body and a conductive body. The ESD safe ceramic body is coupled to a surface of the conductive body by an adhesive, which may be resistant to high temperatures. A plurality of springs are present within the adhesive and extend from the surface of the conductive body to a surface of the ESD safe ceramic body. For example, first ends of the plurality of springs are electrically coupled to the surface of the conductive body, and second ends of the plurality of springs, which are opposite to corresponding ones of the first ends of the plurality of springs, are electrically coupled to the surface of the ESD safe ceramic body. The plurality of springs form electrical pathways such that the ESD safe ceramic body is electrically coupled to the conductive body.

SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE (18358517)

Main Inventor

Yi-Fam Shiu

SEMICONDUCTOR PROCESSING METHOD AND APPARATUS (18447519)

Main Inventor

Shuang-Shiuan DENG

Brief explanation

The abstract describes a method for securing a wafer to an electrostatic chuck in an apparatus and processing the wafer while it is secured. 

• The method involves positioning the wafer on the electrostatic chuck.
• The wafer is secured to the electrostatic chuck by applying different voltages to different regions of the wafer and chuck at different times.
• This allows for precise and controlled securing of the wafer to the chuck.
• The wafer can then be processed by the apparatus while it remains securely attached to the chuck.

Abstract

A method includes: positioning a wafer on an electrostatic chuck of an apparatus; and securing the wafer to the electrostatic chuck by: securing a first wafer region of the wafer to a first chuck region of the electrostatic chuck by applying a first voltage at a first time. The method further includes securing a second wafer region of the wafer to a second chuck region of the electrostatic chuck by applying a second voltage at a second time different from the first time; and processing the wafer by the apparatus while the wafer is secured to the electrostatic chuck.

SYSTEM AND METHOD FOR RING FRAME CLEANING AND INSPECTION (18231751)

Main Inventor

Chien-Fa Lee

Brief explanation

- The patent application describes a system and method for cleaning ring frames.

- The system includes multiple blades that are used to mechanically remove tapes and tape residues from the surfaces of a ring frame. - It also includes multiple wheel brushes that are used to condition the surfaces of the ring frame. - A transport mechanism is provided to transport the ring frame during the cleaning process. - The purpose of the invention is to provide an efficient and effective way to clean ring frames, which are used in various industries such as textile manufacturing. - The system and method described in the patent application can help improve the performance and longevity of ring frames by removing tapes and residues that can negatively impact their operation. - The use of blades and wheel brushes provides a mechanical cleaning process that is more thorough and precise compared to traditional cleaning methods. - The transport mechanism ensures that the ring frame is moved through the cleaning process smoothly and efficiently. - Overall, the invention aims to enhance the cleaning process for ring frames, leading to improved productivity and reduced maintenance requirements.

Abstract

A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.

SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF (18446549)

Main Inventor

Soon-Kang HUANG

ETCH METHOD FOR INTERCONNECT STRUCTURE (18447134)

Main Inventor

Chun-Cheng Chou

LOCAL INTERCONNECT (18447549)

Main Inventor

Cheng-Hsien Wu

SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME (18230338)

Main Inventor

Ting-Ya LO

FINFET STRUCTURE WITH CONTROLLED AIR GAPS (18360617)

Main Inventor

Wen-Che Tsai

Brief explanation

The abstract describes an integrated circuit (IC) structure that includes two fins on a semiconductor substrate, separated by an isolation feature made of a dielectric material. There is also a contact feature between the fins that extends into the isolation feature, creating an air gap between them. The dielectric material extends from the substrate to the contact feature.

• IC structure with two fins on a semiconductor substrate
• Fins are separated by an isolation feature made of dielectric material
• Contact feature between the fins extends into the isolation feature
• Air gap is created between the isolation feature and the contact feature
• Dielectric material extends from the substrate to the contact feature

Abstract

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

Semiconductor Device with Air Gaps and Method of Fabrication Thereof (18446183)

Main Inventor

Chia-Hao Chang

Brief explanation

The patent application describes a semiconductor structure that includes various components such as epitaxial features, a semiconductor channel layer, a gate structure, a backside metal wiring layer, and a backside conductive contact. 

• The semiconductor structure has first and second epitaxial features, a semiconductor channel layer, and a gate structure at the frontside.
• A backside metal wiring layer is present at the backside of the semiconductor structure.
• A backside conductive contact connects the first epitaxial feature to the backside metal wiring layer.
• There is an air gap between the backside metal wiring layer and the gate structure.

Abstract

A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

Integrated Circuit Package and Method (18446521)

Main Inventor

Ting-Chen Tseng

Brief explanation

The patent application describes a method for fabricating a semiconductor device with multiple metallization patterns and dielectric layers.

• The method begins by dispensing a first dielectric layer around and on a first metallization pattern, using a photoinsensitive molding compound.
• The first dielectric layer is then planarized to create a smooth surface.
• A second metallization pattern is formed on top of the first dielectric layer and the first metallization pattern.
• A second dielectric layer is dispensed around the second metallization pattern and on the first dielectric layer, using a photosensitive molding compound.
• The second dielectric layer is patterned to create openings that expose portions of the second metallization pattern.
• A third metallization pattern is formed on top of the second dielectric layer and in the openings, connecting to the exposed portions of the second metallization pattern.

Abstract

In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

Semiconductor Package Including Step Seal Ring and Methods Forming Same (17819341)

Main Inventor

Sheng-Han Tsai

Brief explanation

The patent application describes a method for forming dielectric layers and metal lines on a semiconductor substrate.

• The method involves forming multiple dielectric layers over the substrate and creating metal lines and vias within these layers.
• The lower portions of both an inner seal ring and an outer seal ring are formed, extending into the dielectric layers.
• A first dielectric layer is then deposited over the metal lines and vias, and an opening is etched through this layer.
• This etching exposes the top surface of the lower portion of the inner seal ring and allows the lower portion of the outer seal ring to be in contact with the bottom surface of the first dielectric layer.
• An upper portion of the inner seal ring is formed to extend into the opening and connect with the lower portion.
• Finally, a second dielectric layer is deposited to cover the upper portion of the inner seal ring.

Overall, the innovation in this patent application lies in the specific method for forming and connecting the inner and outer seal rings within the dielectric layers, providing improved sealing and protection for the semiconductor substrate.

Abstract

A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.

Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices (18359486)

Main Inventor

Shih-Kang Fu

Brief explanation

The patent application describes a semiconductor structure with specific features and arrangements.

• The structure includes a contact on a substrate and an interlayer dielectric (ILD) layer.
• The ILD layer has two regions: a first region directly above the contact and a second region adjacent to the first region.
• The first region contains embedded first conductive features that are separated by a certain distance.
• A dielectric layer is embedded in the ILD layer and is located between the first conductive features in the first region.
• The second region does not have the dielectric layer and instead contains second conductive features that are separated by a greater distance than the first conductive features.

The innovation in this patent application is the specific arrangement and configuration of the semiconductor structure, which includes separate regions with different conductive features and distances between them.

Abstract

A semiconductor structure includes a contact over a substrate, an interlayer dielectric (ILD) layer including a first region disposed directly above the contact and a second region disposed adjacent to the first region, first conductive features embedded in the first region and separated by a first distance, a dielectric layer embedded in the ILD layer and disposed between the first conductive features in the first region, and second conductive features disposed in the second region and separated by a second distance greater than the first distance. The second region is free of the dielectric layer.

IMPROVED CONTACT RESISTANCE BETWEEN VIA AND CONDUCTIVE LINE (18447084)

Main Inventor

Chun-Yuan Chen

Brief explanation

The patent application describes a method for forming conductive features on a substrate using a Chemical Mechanical Polishing (CMP) process and an Interlayer Dielectric (ILD) layer. 

• A first conductive feature is formed on a substrate.
• A via is created to connect with the first conductive feature, using a conductive material.
• The top surface of the via is polished using a CMP process.
• An ILD layer is deposited on the via.
• A trench is formed within the ILD layer to expose the via.
• The trench is filled with a second conductive feature that also connects with the via, using the same material as the conductive material.

Abstract

A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Contact Structure For Semiconductor Device (18232718)

Main Inventor

Hsu-Kai CHANG

Brief explanation

- The patent application describes a semiconductor structure and a method for forming it.

- The structure includes a substrate, a gate structure, a source/drain contact structure, a layer of dielectric material, a layer of organometallic material, and a trench conductor layer. - The organometallic material is located between the dielectric material and the trench conductor layer. - The method involves forming the various layers and structures in a specific sequence to create the semiconductor structure. - The invention aims to improve the performance and functionality of semiconductor devices.

Abstract

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

SOURCE/DRAIN CONTACT FORMATION METHODS AND DEVICES (18361770)

Main Inventor

Cheng-Wei Chang

Brief explanation

The patent application describes a semiconductor device with specific layers and materials.

• The device includes a substrate and two semiconductor fins protruding from the substrate.
• An epitaxial feature connects the two semiconductor fins.
• A silicide layer is placed over the epitaxial feature.
• A barrier layer, made of a metal nitride, is placed over the silicide layer.
• A metal layer is placed over the barrier layer.
• The atomic ratio of oxygen to metal nitride at the boundary between the barrier layer and the metal layer is between 0.15 and 1.0.

Abstract

A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.

METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES (17825307)

Main Inventor

Yu-Chen KO

METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH (17825678)

Main Inventor

Chung-Liang CHENG

GATE CONTACT STRUCTURE (18446326)

Main Inventor

Cheng-Chi Chuang

METHOD OF FORMING CONTACT METAL (18360587)

Main Inventor

Chun-Hsien Huang

Brief explanation

The abstract describes a semiconductor device and its components.

• The device includes a source/drain feature, which is a part of the device that allows current to flow in and out.
• A dielectric layer is formed over the source/drain feature, which is an insulating layer that separates different components of the device.
• A contact trench is formed through the dielectric layer to expose the source/drain feature, allowing for electrical connections to be made.
• A titanium nitride (TiN) layer is deposited in the contact trench, which is a material that helps improve the conductivity and stability of the device.
• A cobalt layer is deposited over the TiN layer in the contact trench, which further enhances the conductivity and performance of the device.

Abstract

A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE (18446748)

Main Inventor

Jiun Yi Wu

Brief explanation

The patent application describes a structure that includes a core substrate and a redistribution structure.

• The structure has multiple redistribution layers, each consisting of a dielectric layer and a metallization layer.
• The structure also includes a local interconnect component embedded in one of the redistribution layers.
• The local interconnect component has a substrate, an interconnect structure, and bond pads.
• The bond pads of the local interconnect component physically contact a metallization layer of another redistribution layer.
• The metallization layer of the other redistribution layer contains conductive vias.
• The dielectric layer of the first redistribution layer encapsulates the local interconnect component.

Abstract

In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.

METAL GATE PROCESS AND RELATED STRUCTURE (17804146)

Main Inventor

Chih-Lun LU

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18446728)

Main Inventor

Chan Syun David Yang

Brief explanation

The patent application describes a semiconductor device called a fin field effect transistor and its manufacturing process.

• Gate spacers are formed over a semiconductor fin.
• A first gate stack is formed over the fin.
• A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack.
• A second sacrificial material with a large selectivity is formed over a source/drain contact plug.
• Etching processes are used to create openings through the first and second sacrificial materials.
• The openings are then filled with a conductive material.

Abstract

A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION (18360814)

Main Inventor

Osamu KOIKE

FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions (18361354)

Main Inventor

Shahaji B. More

Brief explanation

The patent application describes a method for forming a semiconductor structure with multiple fins.

• The method involves creating two groups of fins, with the first group being farther away from the second group.
• The first group of fins includes three fins, with the third fin being the closest to the second group.
• An epitaxy process is then performed to form an epitaxy region based on these fins.
• The epitaxy region consists of two portions, with the first portion located between the first and second fins and the second portion between the second and third fins.
• The first portion has a higher top surface than the second portion.

Abstract

A method includes forming a first fin-group having has a plurality of semiconductor fins, and a second fin-group. The plurality of semiconductor fins include a first semiconductor fin, which is farthest from the second fin-group among the first fin-group, a second semiconductor fin, and a third semiconductor fin, which is closest to the second fin-group among the first fin-group. The method further includes performing an epitaxy process to form an epitaxy region based on the plurality of semiconductor fins. The epitaxy region includes a first portion and a second portion. The first portion is in middle between the first semiconductor fin and the second semiconductor fin. The first portion has a first top surface. The second portion is in middle between the second semiconductor fin and the third semiconductor fin. The second portion has a second top surface lower than the first top surface.

Semiconductor Device With Isolation Structures (18232171)

Main Inventor

Pei-Wei Lee

Brief explanation

The patent application describes a method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure.

• The method involves several steps to create the desired structure:
• An etch stop layer is formed on a substrate.
• A superlattice structure is formed on top of the etch stop layer.
• An isolation layer is deposited on the superlattice structure.
• A semiconductor layer is deposited on the isolation layer.
• A bi-layer isolation structure is formed on the semiconductor layer.
• The substrate and etch stop layer are removed.
• The superlattice structure, isolation layer, semiconductor layer, and bi-layer isolation structure are etched to form a fin structure.
• A gate-all-around structure is formed on the fin structure.

The innovation lies in the use of superlattice structures and an embedded isolation structure to create a semiconductor device.

Abstract

A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.

Semiconductor Device and Method of Manufacture (18363945)

Main Inventor

Chia-Ching Lee

Brief explanation

The patent application describes a method for forming a gate structure in a semiconductor device.

• A recess is created between adjacent gate spacers by removing a dummy gate electrode and a dummy gate dielectric.
• A gate dielectric is then deposited in the recess.
• A barrier layer is deposited over the gate dielectric.
• A first work function layer is deposited over the barrier layer.
• A first anti-reaction layer is formed over the first work function layer to reduce oxidation of the first work function layer.
• A fill material is deposited over the first anti-reaction layer.

Abstract

A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Local Gate Height Tuning by CMP and Dummy Gate Design (18365405)

Main Inventor

Ming-Chang Wen

Brief explanation

- The patent application describes a method for fabricating devices with tunable gate height and effective capacitance.

- The method involves forming two different metal gate stacks, one in a dummy region and one in an active device region of a semiconductor substrate. - A chemical mechanical polishing (CMP) process is then performed using a slurry containing charged abrasive nanoparticles. - The charged abrasive nanoparticles have different concentrations in the active device region and the dummy region. - The innovation allows for the precise control of gate height and effective capacitance in fabricated devices.

Abstract

The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE (18361501)

Main Inventor

Chung-Ting KO

MULTI-LAYERED INSULATING FILM STACK (18363439)

Main Inventor

Chieh-Ping Wang

Brief explanation

The patent application describes a method for forming a semiconductor device.

• The method involves forming a gate structure over a fin that protrudes above a substrate.
• An opening is then formed in the gate structure.
• A non-conformal first dielectric layer is formed along the sidewalls and bottom of the opening.
• The first dielectric layer has a larger thickness near the upper surface of the gate structure and a smaller thickness near the bottom of the opening.
• A second dielectric layer, made of a different material, is then formed over the first dielectric layer to fill the opening.

Abstract

A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18447125)

Main Inventor

Shu-Uei Jang

Self-Aligned Structure For Semiconductor Devices (18447922)

Main Inventor

Kuo-Cheng CHIANG

Brief explanation

- The patent application is about a semiconductor device and its manufacturing method.

- The device includes self-aligned isolation structures, which are used to separate different components of the device. - These self-aligned isolation structures are formed by depositing dielectric material in openings or replacing portions of fins with dielectric material. - The separation between these self-aligned isolation structures is determined by the photolithography process used, and it is equal to or larger than the separation of the active fins. - The purpose of these self-aligned isolation structures is to improve the performance and functionality of the semiconductor device.

Abstract

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME (17824249)

Main Inventor

Ta-Chun LIN

Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof (18366562)

Main Inventor

Wei-Sheng Yun

Brief explanation

The patent application describes a semiconductor structure with a fin on a substrate, consisting of vertically stacked channels made of germanium.

• The fin has a channel region with multiple channels, and a gate stack and gate spacers are used to control the flow of current.
• Each channel has a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers.
• The concentration of germanium in the middle section is higher than in the end sections.
• The middle section of the channel has a core portion and an outer portion with a germanium concentration profile.

Abstract

A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES (18359747)

Main Inventor

Yu-Jen Shen

HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER (18447239)

Main Inventor

Huiching Chang

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (17824263)

Main Inventor

Chih-Hsin Yang

MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION (18359206)

Main Inventor

I-Che Lee

DEPOSITION SYSTEM AND METHOD (18361729)

Main Inventor

Wen-Hao CHENG

Brief explanation

- The abstract describes a deposition system that can measure film characteristics such as thickness, resistance, and composition.

- The system includes a substrate process chamber, a substrate pedestal to support the substrate, and a target enclosing the chamber. - A shutter disk with an in-situ measuring device is provided in the system. - The measuring device allows for real-time measurement of film characteristics during the deposition process. - This innovation enables better control and monitoring of the deposition process, leading to improved film quality and efficiency.

Abstract

A deposition system is provided capable of measuring at least one of the film characteristics (e.g., thickness, resistance, and composition) in the deposition system. The deposition system in accordance with the present disclosure includes a substrate process chamber. The deposition system in accordance with the present disclosure includes a substrate pedestal in the substrate process chamber, the substrate pedestal configured to support a substrate, and a target enclosing the substrate process chamber. A shutter disk including an in-situ measuring device is provided.

SYSTEMS AND METHODS OF TESTING MEMORY DEVICES (18232518)

Main Inventor

Meng-Han Lin

SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE (18232520)

Main Inventor

Tsung-Yang Hsieh

SEMICONDUCTOR DEVICE AND METHOD (18446591)

Main Inventor

Yin-Jie Pan

Brief explanation

- The patent application describes a semiconductor device and a method of manufacturing it.

- The device is made using a channel-less, porous low K material. - The material is created by combining a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. - The material is then cured to remove a porogen and collapse channels within it. - This allows the material to be formed with a scaling factor of less than or equal to about 1.8.

Abstract

A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.

Package and Method for Forming the Same (17828691)

Main Inventor

Yu-Sheng Lin

Brief explanation

The patent application describes a package design for a semiconductor device.

• The package includes a redistribution structure with a dielectric layer and a conductive element.
• A semiconductor device is bonded to the redistribution structure, and it has a corner.
• An underfill material is applied over the redistribution structure, and it has a protrusion that extends into the dielectric layer.
• The protrusion of the underfill material overlaps the corner of the semiconductor device in a plan view.

Abstract

In an embodiment, a package including: a redistribution structure including a first dielectric layer and a first conductive element disposed in the first dielectric layer; a first semiconductor device bonded to the redistribution structure, wherein the first semiconductor device includes a first corner; and an underfill disposed over the redistribution structure and including a first protrusion extending into the first dielectric layer of the redistribution structure, wherein the first protrusion of the underfill overlaps the first corner of the first semiconductor device in a plan view.

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME (18447416)

Main Inventor

Ting-Chen Tseng

Brief explanation

The abstract describes a package and method for an integrated circuit die. The package includes an integrated circuit die with two different sloped facets on its sidewall. The die is surrounded by an encapsulant and an insulating layer. The upper surface of the die is lower than the upper surface of the encapsulant, and the sidewall of the insulating layer is coplanar with one of the facets.

• Package and method for an integrated circuit die
• Integrated circuit die has two different sloped facets on its sidewall
• Die is surrounded by an encapsulant and an insulating layer
• Upper surface of the die is lower than the upper surface of the encapsulant
• Sidewall of the insulating layer is coplanar with one of the facets

Abstract

A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE (18363742)

Main Inventor

Meng-Liang Lin

STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE (18446076)

Main Inventor

Jen-Yuan CHANG

SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING (18447927)

Main Inventor

Jian WU

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (17827992)

Main Inventor

Wei-Ming Wang

INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME (17829243)

Main Inventor

Chang-Jung HSUEH

VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS (17825336)

Main Inventor

Ting-Yu Yeh

Through-Circuit Vias In Interconnect Structures (18232200)

Main Inventor

Jian-Hong LIN

Brief explanation

The abstract describes an integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same.

• The IC includes a semiconductor device and interconnect structures on its surfaces.
• It also includes inter-layer dielectric (ILD) layers on the front and back surfaces of the substrate.
• The TCV is a conductive pathway that goes through the interconnect structures, ILD layers, and substrate.
• The TCV is separated from the semiconductor device by a portion of the substrate and portions of the ILD layers.
• One end of the TCV is connected to a conductive line in the first interconnect structure, while the other end is connected to a conductive line in the second interconnect structure.

Abstract

An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (18361917)

Main Inventor

Jen-Chun Liao

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18446146)

Main Inventor

Chen-Hua Yu

Brief explanation

The abstract describes a method for forming package structures, specifically for placing a first package within a recess of a first substrate and attaching a first sensor to the first package and substrate.

• The method involves placing a first package containing a first die into a recess of a first substrate.
• A first sensor is then attached to both the first package and the first substrate.
• The first sensor is electrically connected to both the first package and the first substrate.

Abstract

Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The first package includes a first die. The method further includes attaching a first sensor to the first package and the first substrate. The first sensor is electrically coupled to the first package and the first substrate.

Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via (18447871)

Main Inventor

Yung-Chi Lin

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18359864)

Main Inventor

Ting-Yu Yeh

Semiconductor Device and Method of Manufacture (18446006)

Main Inventor

Jiun Yi Wu

Brief explanation

The patent application describes a package design for electronic devices.

• The package includes multiple layers of molding material and metallization layers.
• Through vias are present within the molding material, connecting the metallization layers.
• Integrated passive devices are embedded within the molding material.
• A redistribution structure is present on top of the metallization layer and molding material.
• The redistribution structure is connected to the through vias and integrated passive devices.
• At least one semiconductor device is mounted on the redistribution structure and connected to it.

Abstract

A package includes a first layer of molding material, a first metallization layer on the first layer of molding material, a second layer of molding material on the first metallization layer and the first layer of molding material, a second metallization layer on the second layer of molding material, through vias within the second layer of molding material, the through vias extending from the first metallization layer to the second metallization layer, integrated passive devices within the second layer of molding material, a redistribution structure electrically on the second metallization layer and the second layer of molding material, the redistribution structure connected to the through vias and the integrated passive devices, and at least one semiconductor device on the redistribution structure, the at least one semiconductor device connected to the redistribution structure.

SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH (18232523)

Main Inventor

Yueh-Ting Lin

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18363766)

Main Inventor

Chien-Hung Chen

Semiconductor Devices Including Decoupling Capacitors (18446648)

Main Inventor

Yu-Xuan Huang

Brief explanation

The patent application describes methods of forming decoupling capacitors in interconnect structures on the backsides of semiconductor devices. These devices include a device layer with a transistor, interconnect structures on both the front and back sides, and a contact that connects to the source/drain region of the transistor. 

• The second interconnect structure on the backside includes a first dielectric layer and a first conductive line connected to the source/drain region of the transistor.
• The second dielectric layer adjacent to the first conductive line has a high k-value (greater than 7.0), which allows for increased capacitance.
• The first conductive line and the second dielectric layer form a decoupling capacitor, which helps to stabilize the power supply voltage and reduce noise in the device.
• This innovation provides a more efficient and compact way of incorporating decoupling capacitors into semiconductor devices, improving their performance and reliability.

Abstract

Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446873)

Main Inventor

Chung-Ting Lu

BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE (18447722)

Main Inventor

Tsung-Chieh Hsiao

SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING (17825698)

Main Inventor

Chih-Yu Lu

SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD (17752704)

Main Inventor

Chi-Yu LU

Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same (18366771)

Main Inventor

Hsien-Wei Chen

Brief explanation

The patent application describes a semiconductor device with multiple layers and interconnects. Here are the key points:

• The device has a substrate as its base.
• A first dielectric layer is placed over the substrate.
• A first interconnect is embedded within the first dielectric layer.
• A second dielectric layer is added on top of the first dielectric layer and the first interconnect.
• A conductive via is created, passing through the first and second dielectric layers and the substrate.
• The top surface of the conductive via is aligned with the top surface of the second dielectric layer.
• A third dielectric layer is applied over the second dielectric layer and the conductive via.
• A fourth dielectric layer is added on top of the third dielectric layer.
• A second interconnect is formed within the fourth dielectric layer.
• The second interconnect physically connects with the first interconnect by passing through the third and second dielectric layers.

Abstract

A semiconductor device includes a substrate. A first dielectric layer is over the substrate. A first interconnect is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and the first interconnect. A conductive via extends through the first dielectric layer, the second dielectric layer and the substrate. A topmost surface of the conductive via is level with a topmost surface of the second dielectric layer. A third dielectric layer is over the second dielectric layer and the conductive via. A fourth dielectric layer is over the third dielectric layer. A second interconnect is in the fourth dielectric layer. The second interconnect extends through the third dielectric layer and the second dielectric layer and physically contacts the first interconnect.

CONDUCTIVE RAIL STRUCTURE FOR SEMICONDUCTOR DEVICES (18447664)

Main Inventor

Yi-Bo LIAO

Brief explanation

- The patent application describes a semiconductor structure and a method for forming it.

- The semiconductor structure includes a substrate, a first vertical structure, and a second vertical structure formed over the substrate. - There is also a conductive rail structure between the first and second vertical structures. - The top surface of the conductive rail structure is aligned with the top surfaces of the first and second vertical structures. - The purpose of this invention is to provide a semiconductor structure with improved conductivity and alignment between different vertical structures.

Abstract

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

DIAGONAL VIA STRUCTURE (18448125)

Main Inventor

Shih-Wei PENG

DUAL-MODE WIRELESS CHARGING DEVICE (18232312)

Main Inventor

Shih-Wei LIANG

Brief explanation

The patent application describes a method of making a semiconductor device.

• The method involves forming a first molding layer on a substrate.
• A first plurality of vias is formed in the first molding layer.
• A first conductive line is formed over the first molding layer, with one end of the line aligning with and being electrically coupled to a first via.
• A second molding layer is formed above the first molding layer.
• A second plurality of vias is formed in the second molding layer, with one via aligning with and being electrically coupled to the other end of the conductive line.
• The second plurality of vias, the conductive line, and the first plurality of vias are all electrically coupled to each other.

Abstract

A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.

SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT (18232306)

Main Inventor

Gerben DOORNBOS

ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY (18446025)

Main Inventor

Shih-Wei Peng

Semiconductor Structures And Methods Of Forming The Same (18446113)

Main Inventor

Lin-Yu Huang

Brief explanation

The patent application describes a method for forming conductive features on a semiconductor substrate. 

• A semiconductor substrate is prepared and a layer of dielectric material is formed on top of it.
• A trench is created in the dielectric layer.
• The trench is filled with a conductive layer, which is then segmented to form two separate conductive features.
• A recess is formed between the two conductive features.
• The recess is filled with a second layer of dielectric material.
• The resulting structure has the conductive features end-capped by portions of the first and second dielectric layers.

Abstract

A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.

FIRST METAL STRUCTURE, LAYOUT, AND METHOD (17752737)

Main Inventor

Chi-Yu LU

Semiconductor Devices Including Backside Power Via and Methods of Forming the Same (17819679)

Main Inventor

Po-Hsien Cheng

Brief explanation

- The patent application describes methods of forming vias in semiconductor devices to connect source/drain regions to backside interconnect structures.

- The semiconductor device includes a conductive feature adjacent a gate structure, a dielectric layer, a metal via embedded in the dielectric layer, and a liner layer between the metal via and the dielectric layer. - The liner layer is made of boron nitride, which helps improve the performance and reliability of the via. - The use of boron nitride as the liner layer provides better electrical insulation and thermal conductivity. - The methods described in the patent application can be used to enhance the overall functionality and efficiency of semiconductor devices.

Abstract

Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS (18361666)

Main Inventor

Chih-Liang CHEN

METHOD OF MANUFACTURING INTEGRATED CIRCUIT (18447572)

Main Inventor

Chih-Yu LAI

CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES (18448005)

Main Inventor

Li-Chun Tien

METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS (18448028)

Main Inventor

Chih-Liang CHEN

Liner-Free Conductive Structures With Anchor Points (18232722)

Main Inventor

Hsu-Kai Chang

Brief explanation

- The patent application describes a method for creating conductive structures without the need for a liner or barrier layer.

- The method involves depositing an etch stop layer on a cobalt contact on a substrate. - A dielectric layer is then deposited on top of the etch stop layer. - The dielectric and etch stop layers are etched to create an opening that exposes the top surface of the cobalt contact. - The exposed top surface of the cobalt contact is etched to create a recess that extends under the etch stop layer. - A ruthenium metal is deposited to fill the recess and the opening. - The ruthenium metal is annealed to form an oxide layer between the ruthenium metal and the dielectric.

Abstract

The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

GRAPHENE LAYER FOR REDUCED CONTACT RESISTANCE (18359383)

Main Inventor

Shin-Yi Yang

Brief explanation

- The patent application describes a method for forming a trench within a dielectric layer.

- The trench consists of an interconnect portion and a via portion that exposes an underlying conductive feature. - A seed layer is deposited within the trench, followed by a carbon layer. - A carbon dissolution process is performed, which causes a graphene layer to form between the seed layer and the underlying conductive feature. - The remaining part of the trench is filled with a conductive material.

Abstract

A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT (18360012)

Main Inventor

Shin-Yi Yang

INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS (17825345)

Main Inventor

Chien Hung Liu

SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE (17825741)

Main Inventor

Hsi-Wen TIEN

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18446753)

Main Inventor

Hung-Ming CHEN

Brief explanation

The patent application describes a method for forming an epitaxy feature in a substrate using a carbon-containing layer and a gate spacer. Here are the key points:

• A gate structure is formed on a substrate.
• A gate spacer is formed on the sidewall of the gate structure.
• A carbon-containing layer is formed on the gate spacer.
• Carbon from the carbon-containing layer diffuses into a portion of the substrate below the gate spacer.
• A recess is formed in the substrate on one side of the gate spacer, opposite to the gate structure.
• An epitaxy feature is formed in the recess of the substrate.

Abstract

A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

DUAL-SIDED ROUTING IN 3D SIP STRUCTURE (18447769)

Main Inventor

Po-Hao Tsai

Brief explanation

A semiconductor package is created by connecting two components together.

• The first component is made by creating a redistribution structure on a substrate.
• A through via is made on the redistribution structure, and a die is attached to it.
• The second component has its own redistribution structure, which is connected to the through via.
• A molding compound is added between the two redistribution structures and around the sides of the second component.

Abstract

A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF (17823063)

Main Inventor

Sheng-Fan YANG

SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION (17824353)

Main Inventor

Shu-Chun Yang

Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via (18232713)

Main Inventor

Kam-Tou SIO

Brief explanation

The patent application describes a semiconductor structure with a power distribution network and various interlayer dielectrics and interconnect layers. 

• The structure includes first and second conductive lines for power distribution.
• The substrate of the structure has a first surface in contact with the power distribution network.
• Backside vias are present in the substrate and connected to the first conductive line.
• A via rail is located on the opposite surface of the substrate.
• The structure includes multiple interlayer dielectrics, including a first, second, and third interlayer dielectric.
• The first interlayer dielectric is on the via rail and substrate.
• The second interlayer dielectric is on top of the first interlayer dielectric.
• The third interlayer dielectric is on top of the second interlayer dielectric.
• The second and third interlayer dielectrics contain first and top interconnect layers, respectively.
• Deep vias are present in the interlayer dielectric and connected to the via rail.
• The deep vias are also connected to the first and top interconnect layers.
• A power supply in/out layer is located on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract

The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME (18230999)

Main Inventor

Cheng-Chieh HSIEH

SEMICONDCUTOR PACKAGES AND METHODS OF FORMING THEREOF (17881128)

Main Inventor

Sung-Yueh Wu

Brief explanation

The abstract describes a semiconductor package that includes an integrated circuit die, an encapsulant surrounding the die, and a fan-out structure that is electrically connected to the die. The fan-out structure has a first opening that extends through it and partially through the encapsulant. The encapsulant completely surrounds the first opening when viewed from the top. The package also includes a package substrate that is bonded to the first package component.

• The semiconductor package includes an integrated circuit die.
• The die is surrounded by an encapsulant.
• The package has a fan-out structure that is electrically connected to the die.
• The fan-out structure has a first opening that extends through it.
• The first opening also partially extends through the encapsulant.
• The encapsulant completely surrounds the first opening when viewed from the top.
• The package substrate is bonded to the first package component.

Abstract

A semiconductor package includes a first package component comprising: an integrated circuit die; an encapsulant surrounding the integrated circuit die; and a fan-out structure electrically connected to the integrated circuit die, wherein a first opening extends completely through the fan-out structure and at least partially through the encapsulant in a cross-sectional view, and wherein the encapsulant at least completely surrounds the first opening in a top-down view. The semiconductor package further includes a package substrate bonded to the first package component.

Antenna Apparatus and Method (18366282)

Main Inventor

Feng-Wei Kuo

Brief explanation

The patent application describes a package structure that includes two dies and an insulating material.

• The first die is connected to the second die, and the second die is surrounded by the insulating material.
• The package structure also includes a first antenna that extends through the insulating material and is connected to the second die.
• The first antenna is located next to a sidewall of the second die.
• The first antenna consists of a conductive plate and multiple conductive pillars that extend through the insulating material.
• The conductive plate is positioned between the conductive pillars and the sidewall of the second die.

Abstract

A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

POLYIMIDE PROFILE CONTROL (18446834)

Main Inventor

Chen-Chi HUANG

Brief explanation

The patent application describes a method for forming a structure with a controlled polyimide profile. 

• The method involves depositing a photoresist containing polyimide onto a substrate and performing a first anneal at a specific temperature.
• A photomask with a pattern representing the desired shape of a polyimide opening is used to expose the photoresist to a radiation source.
• After exposure, a second anneal is performed at a different temperature, and a portion of the photoresist is removed to create the polyimide opening.
• Finally, a third anneal is conducted at another temperature, and the polyimide opening is cleaned through a process called ashing.

Abstract

A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

BONDING STRUCTURES OF INTEGRATED CIRCUIT DEVICES AND METHOD FORMING THE SAME (18446028)

Main Inventor

Chen-Yu Tsai

Brief explanation

The patent application describes a method for forming a conductive pad on a wafer and then etching a dielectric layer to create an opening. The method includes a wet-cleaning process and the deposition of a conductive diffusion barrier and conductive material.

• Method for forming a conductive pad on a wafer and etching a dielectric layer to create an opening
• Includes a wet-cleaning process during which a chemical solution is used to clean the wafer
• Conductive diffusion barrier is deposited to extend into the opening
• Conductive material is deposited over the conductive diffusion barrier

Abstract

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

INTEGRATED CIRCUIT PACKAGE AND METHOD (18365362)

Main Inventor

Wen-Chih Chiou

Brief explanation

The patent application describes a device that includes an interposer, two integrated circuit devices, a buffer layer, and an encapsulant.

• The interposer is a component that connects the integrated circuit devices.
• The first and second integrated circuit devices are bonded to the interposer using dielectric-to-dielectric and metal-to-metal bonds.
• A buffer layer surrounds the integrated circuit devices and is made of a stress reduction material with a lower Young's modulus.
• An encapsulant surrounds the buffer layer, integrated circuit devices, and interposer, and is made of a molding material with a higher Young's modulus.
• The purpose of the buffer layer is to reduce stress on the integrated circuit devices.
• The encapsulant provides protection and stability to the overall device.
• The difference in Young's modulus between the buffer layer and the encapsulant ensures that the stress reduction material absorbs more stress than the molding material.

Abstract

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

SEMICONDUCTOR DIE PACKAGE AND METHOD OF MANUFACTURE (18446732)

Main Inventor

Kuan-Yu Huang

Brief explanation

The patent application describes an interposer with multiple integrated circuit devices attached to it using conductive connectors. 

• The interposer has a first side and a first integrated circuit device attached to it with a set of conductive connectors.
• The conductive connectors have different heights.
• A dummy conductive connector is placed between the interposer and the integrated circuit device.
• An underfill material is used beneath the integrated circuit device and the interposer.
• An encapsulant material is used to surround the integrated circuit device and the interposer.

Abstract

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME (17664689)

Main Inventor

Yu-Sheng Lin

Brief explanation

The patent application describes a package that includes a package substrate, a package component, and warpage control structures.

• The package substrate has a first side and a second side.
• The package component is bonded to the first side of the package substrate.
• A front-side warpage control structure is attached to the first side of the package substrate.
• A backside warpage control structure is embedded in the package substrate from the second side.
• The front-side warpage control structure includes two disconnected structures separated by a gap.
• The backside warpage control structure includes two disconnected structures separated from each other.

Abstract

A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

Storage Layers For Wafer Bonding (18447968)

Main Inventor

De-Yang CHIOU

Brief explanation

- The patent application describes a semiconductor structure that consists of bonded wafers with storage layers.

- The structure includes a first wafer with a storage layer containing carbon, and a second wafer with a storage layer also containing carbon. - A bonding layer is placed between the first and second wafers, making contact with the storage layers. - The purpose of this invention is to provide a method for bonding wafers with storage layers in a semiconductor structure. - The use of carbon in the storage layers is likely to have specific advantages or benefits, although these are not mentioned in the abstract. - The bonding layer plays a crucial role in ensuring the proper connection between the wafers and their storage layers.

Abstract

The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.

System and Method for Bonding Semiconductor Devices (18359416)

Main Inventor

Kai-Tai Chang

Brief explanation

The patent application describes a method for aligning and bonding two wafers in semiconductor manufacturing. Here are the key points:

• The method involves aligning alignment marks on two sides of a first wafer and a second wafer.
• The first offset between the alignment marks on the first wafer is determined.
• The first alignment mark of the first wafer is aligned to a third alignment mark on the first side of the second wafer.
• The location of the second alignment mark of the first wafer is detected to determine the location of the first alignment mark.
• The first wafer is repositioned based on the determined location of the first alignment mark to align it with the third alignment mark.
• Finally, the first side of the first wafer is bonded to the first side of the second wafer to create a bonded structure.

Abstract

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS (17824330)

Main Inventor

Fong-yuan Chang

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18361953)

Main Inventor

Chung-Liang CHENG

System Formed Through Package-In-Package Formation (18362649)

Main Inventor

Chen-Hua Yu

Brief explanation

The patent application describes a package that includes multiple device dies bonded together through hybrid bonding.

• The package consists of a first device die and a second device die, with the second die being larger than the first die.
• The first device die is encapsulated within a first isolation region.
• The first device die, second device die, and first isolation region together form a first package.
• A third device die, larger than the first package, is bonded to the first package through hybrid bonding.
• The third device die is encapsulated within a second isolation region.
• The first package, third device die, and second isolation region together form a second package.

Abstract

A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding. The second device die is larger than the first device die. A first isolation region encapsulates the first device die therein. The first device die, the second device die, and the first isolation region form parts of a first package. A third device die is bonded to the first package through hybrid bonding. The third device die is larger than the first package. A second isolation region encapsulates the first package therein. The first package, the third device die, and the second isolation region form parts of a second package.

Semiconductor Devices and Methods of Manufacturing (18446291)

Main Inventor

Chang-Yi Yang

Brief explanation

The patent application describes a method for assembling and encapsulating semiconductor devices using a redistribution structure and conductive material. 

• The method involves forming a redistribution structure with metallization patterns.
• A semiconductor device is attached to one side of the redistribution structure.
• The semiconductor device is encapsulated with a first encapsulant.
• Openings are formed in the first encapsulant to expose the metallization pattern.
• A conductive material, such as a conductive paste, is filled in the openings.
• Integrated devices are attached to the other side of the redistribution structure.
• The integrated devices are encapsulated with a second encapsulant.
• A pre-solder material is formed on the conductive material after encapsulating the integrated devices.

Abstract

A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.

Integrated Circuit Packages and Methods of Forming the Same (17828310)

Main Inventor

Pei-Haw Tsao

Brief explanation

The abstract describes a method for forming an integrated circuit package. Here are the key points:

• The method involves attaching a first carrier to a package component.
• The package component includes an interposer, a first semiconductor die, a second semiconductor die, an encapsulant, and conductive connectors.
• A second carrier is attached to a package substrate, which has bond pads.
• The conductive connectors of the package component are bonded to the bond pads of the package substrate by reflowing the conductive connectors.
• This bonding process occurs while the first carrier is attached to the package component and the second carrier is attached to the package substrate.
• After bonding, the first carrier and the second carrier are removed.

Abstract

In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME (18447979)

Main Inventor

Te-Hsin CHIU

Stacked Semiconductor Device and Method (18359578)

Main Inventor

Min-Feng Kao

Brief explanation

The patent application describes a semiconductor device and a method of forming it.

• The device includes a first substrate, a capacitor, a diode structure, and a first interconnect structure.
• The capacitor and diode structure are located within the first substrate.
• The first interconnect structure is positioned over the capacitor and diode structure.
• A first conductive via of the first interconnect structure connects the capacitor to the diode structure.

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

SEMICONDUCTOR DEVICE (18362030)

Main Inventor

Chung-Te LIN

Brief explanation

The patent application describes a method for fabricating transistors on a wafer using epitaxial growth and bonding techniques. 

• The method involves growing an epitaxial layer on a first region of a wafer while leaving a second region exposed.
• A first dielectric layer is then formed over the epitaxial layer and the second region.
• A first transistor is formed on a separate wafer.
• A second dielectric layer is formed over the first transistor.
• The first and second dielectric layers are bonded together.
• Finally, second and third transistors are formed on the epitaxial layer and the second region of the first wafer, respectively.

Abstract

A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

INTEGRATED CIRCUIT WITH BACKSIDE TRENCH FOR METAL GATE DEFINITION (18447881)

Main Inventor

Kuo-Cheng CHIANG

Brief explanation

The patent application describes an integrated circuit that includes two nanosheet transistors on a substrate.

• The nanosheet transistors have gate electrodes.
• A gate isolation structure is present on the backside of the substrate.
• The gate isolation structure physically and electrically isolates the gate electrodes from each other.

Abstract

An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

Profile Control Of Gate Structures In Semiconductor Devices (18232181)

Main Inventor

Kai-Chi WU

Brief explanation

The patent application describes an integrated circuit (IC) that includes active and dummy device cell arrays and a method of fabricating the same.

• The IC consists of a substrate, an active device cell, and a dummy device cell.
• The active device cell has an array of source/drain (S/D) regions of a first conductivity type on or within the substrate.
• The active device cell also has an array of gate structures with a first gate fill material on the substrate.
• The dummy device cell includes a first array of S/D regions of the first conductivity type on or within the substrate.
• The dummy device cell also includes a second array of S/D regions of a second conductivity type on or within the substrate.
• The dummy device cell further includes an array of dual gate structures on the substrate.
• Each dual gate structure in the dummy device cell has the first gate fill material and a second gate fill material that is different from the first gate fill material.

Abstract

An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses. The IC includes a substrate, an active device cell, and a dummy device cell. The active device cell includes an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures with a first gate fill material disposed on the substrate. The dummy device cell includes a first array of S/D regions of the first conductivity type disposed on or within the substrate, a second array of S/D regions of a second conductivity type disposed on or within the substrate, and an array of dual gate structures disposed on the substrate. Each of the dual gate structures includes the first gate fill material and a second gate fill material that is different from the first gate fill material.

Semiconductor Device and Method (18359492)

Main Inventor

Jen-Chih Hsueh

Brief explanation

The patent application describes a method for forming semiconductor fins and gate structures in a substrate.

• The method involves creating two semiconductor fins adjacent to each other in the substrate.
• A dummy gate structure is formed over the semiconductor fins.
• A first dielectric material is deposited around the dummy gate structure.
• The dummy gate structure is replaced with a metal gate structure.
• An etching process is performed on the metal gate structure and the first dielectric material to create recesses.
• The recesses extend into the substrate and are located between the semiconductor fins.
• A second dielectric material is deposited within the recesses.

Abstract

A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES (18360007)

Main Inventor

JHON JHY Liaw

Brief explanation

The patent application describes a method for forming a fin protruding from a substrate and creating gate structures across the fin. 

• The first gate structure faces the second gate structure, and a segment of the fin between the gate sidewalls is recessed to form a trench.
• A dielectric layer is then deposited over the gate sidewalls and within the trench.
• An inter-layer dielectric layer is also deposited over the gate structures and the dielectric layer.
• A portion of the inter-layer dielectric layer is located within the trench.

Abstract

A method includes forming a fin protruding from a substrate, forming first and second gate structures across the fin, the first gate structure having a first gate sidewall facing the second gate structure, the second gate structure having a second gate sidewall facing the first gate structure, recessing a segment of the fin between the first and second gate sidewalls to form a trench, depositing a dielectric layer over the first and second gate sidewalls and within the trench, and depositing an inter-layer dielectric layer over the first and second gate structures and over the dielectric layer. A portion of the inter-layer dielectric layer is within the trench.

Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same (18360166)

Main Inventor

Ta-Chun Lin

Brief explanation

The patent application describes a semiconductor device with multiple nanostructures stacked on a substrate and a fin protruding from the substrate.

• The device includes a substrate with two regions - a first region and a second region.
• Multiple nanostructures are vertically stacked above the first region of the substrate.
• Each nanostructure is wrapped by a first gate dielectric layer.
• A first gate electrode layer is placed on top of the first gate dielectric layer.
• The second region of the substrate has a fin protruding from it.
• The fin is made up of alternating first and second semiconductor layers with different material compositions.
• A second gate dielectric layer is placed on the top and sidewall surfaces of the fin.
• A second gate electrode layer is placed on top of the second gate dielectric layer.
• The first gate dielectric layer is thinner than the second gate dielectric layer.

Abstract

A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.

Backside Power Rail And Methods Of Forming The Same (18360895)

Main Inventor

Huan-Chieh Su

Brief explanation

The patent application describes a semiconductor device that includes several components and features. 

• The device has a bottom dielectric feature on a substrate.
• There are multiple channel members directly positioned over the bottom dielectric feature.
• Each of the channel members is wrapped around by a gate structure.
• The device also includes two first epitaxial features that sandwich the bottom dielectric feature in a specific direction.
• Additionally, there are two second epitaxial features that sandwich the plurality of channel members in the same direction.

Abstract

A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME (17826604)

Main Inventor

Yi-Ruei JHAN

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18229682)

Main Inventor

Jui-Chien HUANG

Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells (18360118)

Main Inventor

Jhon Jhy Liaw

Brief explanation

- This patent application describes an integrated circuit (IC) and its manufacturing method.

- The IC includes different types of transistors, specifically gate-all-around (GAA) transistors and fin-like field effect transistors (FinFETs). - The IC has a first region where a first cell with one or more first type GAA transistors is located. - Adjacent to the first cell is a second cell with one or more second type GAA transistors, which are different from the first type. - The first type GAA transistors can be either nanosheet transistors or nanowire transistors, while the second type GAA transistors are the other one of the two. - The IC also has a second region where one or more FinFETs are located, and this region is separated from the first region by a distance. - The integration layout and manufacturing method of this IC are disclosed in the patent application.

Abstract

Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.

SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME (18361704)

Main Inventor

Kuan-Ting Pan

Brief explanation

- The patent application describes a method for fabricating a structure with two fins extending from a substrate.

- The structure includes an isolation structure to separate the bottom portions of the fins, source/drain features over each fin, and a dielectric fin placed between the two fins and over the isolation structure. - A dummy gate stack is then added over the isolation structure, fins, and dielectric fin, followed by one or more dielectric layers on the sidewalls of the dummy gate stack. - The method involves removing the dummy gate stack to create a gate trench within the dielectric layers, exposing the dielectric fin in the trench. - The dielectric fin is then trimmed to reduce its width. - After the trimming, a high-k metal gate is formed in the gate trench.

Abstract

A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18362862)

Main Inventor

Yu-Lien HUANG

SEMICONDUCTOR DEVICE AND METHOD (18365391)

Main Inventor

Shahaji B. More

Brief explanation

The patent application describes an embodiment device that includes several components: 

• An isolation region on a substrate
• A first fin that extends above the top surface of the isolation region
• A gate structure on the first fin
• An epitaxial source/drain region adjacent to the gate structure

The epitaxial source/drain region has two parts:

• A first main portion that is located in the first fin
• A first projecting portion that is located on a sidewall of the first fin and beneath the top surface of the isolation region

This embodiment device aims to improve the performance and functionality of the device by utilizing the specific arrangement and structure of the epitaxial source/drain region.

Abstract

An embodiment device includes: an isolation region on a substrate; a first fin extending above a top surface of the isolation region; a gate structure on the first fin; and an epitaxial source/drain region adjacent the gate structure, the epitaxial source/drain region having a first main portion and a first projecting portion, the first main portion disposed in the first fin, the first projecting portion disposed on a first sidewall of the first fin and beneath the top surface of the isolation region.

SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED BACKSIDE POWER RAIL (18366004)

Main Inventor

Kuo-Cheng Chiang

Brief explanation

The abstract describes a semiconductor structure with specific features and components. 

• The structure includes a substrate with a frontside and a backside.
• An active region is extruded from the substrate and surrounded by an isolation feature.
• A gate stack is formed on the front side of the substrate and placed on the active region.
• Two source/drain (S/D) features are formed on the active region and separated by the gate stack.
• A frontside contact feature is located on the top surface of the first S/D feature.
• A backside contact feature is located on the bottom surface of the second S/D feature and is electrically connected to it.
• A semiconductor layer is placed on the bottom surface of the first S/D feature and the bottom surface of the gate stack.
• The semiconductor layer has a greater thickness on the bottom surface of the gate stack compared to the bottom surface of the first S/D feature.

Abstract

The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17828981)

Main Inventor

Chin-Wei HSU

INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS (18362868)

Main Inventor

Tian-Yu XIE

Brief explanation

The abstract describes an integrated circuit (IC) structure with specific components and their arrangements.

• The IC structure includes two gates, two source regions, a shared drain region, and an isolation region.
• The first gate has two portions extending in different directions, and the same is true for the second gate.
• The shared drain region connects the first portions of both gates.
• The first source region is separated from the shared drain region by the first gate, and the same is true for the second source region and the second gate.
• The isolation region is located between the first portions of both gates and has a quadrilateral pattern that borders the shared drain region.

Abstract

An IC structure includes first and second gates, first and second source regions, a shared drain region, and an isolation region. The first gate has a first portion extending along a first direction and a second portion extending along a second direction. The second gate has a first portion extending along the first direction and a second portion extending along the second direction. The shared drain region extends from the first portion of the first gate to the first portion of the second gate. The first source region is spaced apart from the shared drain region by the first gate. The second source region is spaced apart from the shared drain region by the second gate. The isolation region is between the first portion of the first gate and the first portion of the second gate, and resembles a quadrilateral pattern bordering the shared drain region.

LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE (18366831)

Main Inventor

Harry-Hak-Lay Chuang

METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE (18360214)

Main Inventor

Ming Chyi Liu

IMAGE SENSOR WITH A HIGH ABSORPTION LAYER (18364662)

Main Inventor

Chien-Chang Huang

PIXEL SENSOR INCLUDING A TRANSFER FINFET (18447340)

Main Inventor

Feng-Chien HSIEH

EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR (18364667)

Main Inventor

Shih-Hsun Hsu

IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION (18446572)

Main Inventor

Hsiang-Lin Chen

METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY (18360966)

Main Inventor

Tsun-Kai Tsao

OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE (17824183)

Main Inventor

Yi-Hsien Chang

IMAGE SENSOR DEVICE (18362866)

Main Inventor

Yun-Wei CHENG

Brief explanation

The patent application describes a device that includes multiple photodiode regions, transistors, deep trench isolation (DTI) structures, and isolation structures within a semiconductor substrate.

• The transistors are located on the front-side surface of the substrate.
• The DTI structures extend from the backside surface of the substrate into the substrate at a certain depth.
• The isolation structures also extend from the backside surface of the substrate into the substrate, but at a shallower depth compared to the DTI structures.
• The isolation structures have a triangular profile when viewed from the backside surface of the substrate.

Abstract

A device includes a plurality of photodiode regions within a semiconductor substrate, a plurality of transistors, a plurality of deep trench isolation (DTI) structures, and a plurality of isolation structures. The transistors are over a front-side surface of the semiconductor substrate. The DTI structures extend a first depth from a backside surface of the semiconductor substrate into the semiconductor substrate. The isolation structures extend a second depth from the backside surface of the semiconductor substrate into the semiconductor substrate. The second depth is less than the first depth. From a plan view, each of the plurality of isolation structures has a triangular profile at the backside surface of the semiconductor substrate.

BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR (18364682)

Main Inventor

Cheng-Ta Wu

DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR (18364734)

Main Inventor

Feng-Chien HSIEH

Anchor Structures And Methods For Uniform Wafer Planarization And Bonding (18232751)

Main Inventor

Chia-Yu Wei

Brief explanation

- The patent application is about anchor structures and methods for forming them in a way that ensures uniform planarization and wafer bonding.

- Anchor structures consist of anchor layers and anchor pads. - Anchor layers are formed on a dielectric layer surface. - Anchor pads are formed in the anchor layer and on the dielectric layer surface. - The material used for the anchor layer is selected to have the same planarization selectivity as the anchor pads and the interconnection material. - Anchor pads ensure a uniform density of structures with the same or similar material.

Abstract

The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.

SYSTEMS AND METHODS FOR SHIELDED INDUCTIVE DEVICES (18232332)

Main Inventor

Feng Wei KUO

Brief explanation

The patent application describes a circuit that includes a transformer, a grounded shield, and a circuit component.

• The transformer is located within a first layer and has an inductive footprint.
• The grounded shield is bounded by the inductive footprint within a second layer, which is separate from the first layer.
• The circuit component is bounded by the inductive footprint within a third layer, which is separate from the second layer.
• The circuit component is connected to the transformer through the second layer.
• The third layer is separated from the first layer by the second layer.

Abstract

In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

INDUCTIVE DEVICE (18447482)

Main Inventor

Wei-Yu CHOU

Resistor Structure (18358557)

Main Inventor

Chih-Fan Huang

A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE (18366156)

Main Inventor

Szu-Hsien Lo

HIGH DENSITY METAL INSULATOR METAL CAPACITOR (18231754)

Main Inventor

Wei Kai SHIH

Brief explanation

The patent application describes semiconductor devices and methods.

• The semiconductor device includes an insulation layer, a first electrode, a second electrode, and an insulator.
• The first electrode and second electrode have sidewalls and a bottom surface in contact with the insulation layer.
• The insulator is formed between the first electrode and the second electrode.
• The insulator is coupled to a sidewall of the first electrode and a sidewall of the second electrode.

Abstract

Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17824436)

Main Inventor

Tsung-Chieh HSIAO

SUPER JUNCTION STRUCTURE (18448013)

Main Inventor

Shuai ZHANG

NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION (18232545)

Main Inventor

Lin-Chen Lu

SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME (18366210)

Main Inventor

Ko-Cheng Liu

SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME (18446665)

Main Inventor

Bwo-Ning Chen

Brief explanation

The patent application describes a semiconductor device and a method for manufacturing it.

• The semiconductor device includes stacked semiconductor layers over a substrate.
• The semiconductor layers are separated from each other and stacked vertically.
• An isolation structure is present around the bottom of the semiconductor stack, separating active regions.
• A metal gate structure is located over the channel region of the semiconductor stack and wraps around each of the semiconductor layers.
• A gate spacer is present over the source/drain region of the semiconductor stack and along the sidewalls of the metal gate structure.
• An inner spacer is located over the source/drain region of the semiconductor stack and along the lower portions of the metal gate structure, wrapping around the edge portions of each semiconductor layer.

Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME (17824329)

Main Inventor

Lin-Yu HUANG

SEMICONDUCTOR DEVICE AND METHOD (18359695)

Main Inventor

Hsin-Yi Lee

Brief explanation

The patent application describes a device with nanostructures on a substrate, including a channel region.

• Nanostructures are present on a substrate, forming a channel region.
• A gate dielectric layer wraps around each nanostructure.
• A first work function tuning layer is on the gate dielectric layer, consisting of a first n-type work function metal, aluminum, and carbon.
• The first n-type work function metal has a lower work function value than titanium.
• A glue layer is on the first work function tuning layer.
• A fill layer is on the glue layer.

Abstract

An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.

GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME (17804751)

Main Inventor

Chi-Ming CHEN

EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION (17824915)

Main Inventor

Chih Sheng Huang

INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE (18363077)

Main Inventor

Hsin Fu Lin

SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF (17752211)

Main Inventor

Jui-Lin CHANG

Semiconductor Gate-All-Around Device (18360080)

Main Inventor

Jhon Jhy Liaw

SILICON-GERMANIUM FINS AND METHODS OF PROCESSING THE SAME IN FIELD-EFFECT TRANSISTORS (18447149)

Main Inventor

Yu-Shan Lu

Brief explanation

The patent application describes a semiconductor structure with a SiGe fin protruding from a substrate.

• SiGe fin has a top portion with two sidewalls and a bottom portion with two other sidewalls.
• The first transition region connects the first sidewall to the third sidewall, and the second transition region connects the second sidewall to the fourth sidewall.
• Both transition regions have a tapered profile extending away from the respective sidewalls.
• A Si-containing layer is placed on the top portion of the SiGe fin.
• The Si-containing layer on the first transition region extends away from the first sidewall by a certain lateral distance.
• The Si-containing layer on the second transition region extends away from the second sidewall by a different lateral distance.

Abstract

A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.

PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS (18361262)

Main Inventor

Meng-Huan Jao

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447053)

Main Inventor

Chun-Hsien Huang

Brief explanation

- The patent application describes methods for forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device.

- The methods involve etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact. - Silicon oxide structures along the sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer are repaired to prevent selective loss defects during subsequent processes. - A selective bottom-up deposition of conductive fill material is performed to form a second source/drain contact. - Once the second source/drain contact is formed, a contact plug can be formed over the gate stack.

Abstract

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

SEMICONDUCTOR DEVICE AND METHOD (18447212)

Main Inventor

Po-Chuan Wang

Brief explanation

The patent application describes a semiconductor device and manufacturing method that use a remote plasma process to minimize material segregation, resulting in a smoother interface for depositing conductive material. This reduces losses and improves overall yield.

• Semiconductor device and manufacturing method using a remote plasma process
• Aims to reduce or eliminate material segregation
• Material segregation can cause uneven interfaces for depositing conductive material
• Smoother interfaces allow for better deposition of conductive material
• Improved deposition reduces losses and improves overall yield

Abstract

A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield.

SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER (18446864)

Main Inventor

Shih-Chuan Chiu

SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF (18360085)

Main Inventor

Po-Yu Huang

SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION (18447344)

Main Inventor

Te-Chih HSIUNG

CONTACT PLUG STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME (18366469)

Main Inventor

Pei-Yu Chou

Brief explanation

The patent application describes a semiconductor device and a method of forming it.

• The device includes a gate stack on a substrate.
• A first dielectric layer made of a first material is placed over the gate stack.
• A second dielectric layer made of a different second material is placed over the first dielectric layer.
• A first conductive feature is located next to the gate stack.
• A second conductive feature is placed on top of and in physical contact with the first conductive feature.
• The bottom surface of the second conductive feature is in physical contact with the top surface of the second dielectric layer.

Abstract

A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

NOVEL STRUCTURE FOR METAL GATE ELECTRODE AND METHOD OF FABRICATION (18446567)

Main Inventor

Ru-Shang Hsiao

Brief explanation

The patent application describes a semiconductor device that includes a transistor with a channel component and a gate component.

• The gate component is made up of several layers, including a dielectric layer, a first work function metal layer, a fill-metal layer, and a second work function metal layer.
• The purpose of these layers is to control the flow of electrical current in the transistor.
• The use of multiple metal layers allows for more precise control of the transistor's performance.
• This design may lead to improved efficiency and performance in semiconductor devices.
• The patent application provides a detailed description of the materials and processes used to create the device.

Abstract

A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

Interconnect Features With Sharp Corners and Method Forming Same (18366352)

Main Inventor

Tze-Liang Lee

Brief explanation

- The patent application describes a method for forming conductive features on a dielectric layer.

- The method involves depositing a dielectric layer and then placing mandrel strips on top of it. - Spacers are formed on the sidewalls of the mandrel strips, creating mask groups. - Each mask group consists of a mandrel strip and two spacers. - A mask strip is formed to connect neighboring mask groups. - The mask groups and mask strip collectively serve as an etching mask to create trenches in the dielectric layer. - The trenches are then filled with a conductive material to form the desired conductive features.

Abstract

A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups. Each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups. The method further includes forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer and to form trenches in the dielectric layer, and filling a conductive material into the trenches to form a plurality of conductive features.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES (17752461)

Main Inventor

Yung-Hsiang CHAN

NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIAL (18365995)

Main Inventor

Chao-Ching Cheng

Brief explanation

- The patent application describes a method for forming a structure on a substrate using sacrificial layers.

- The method involves creating a sandwich structure with a two-dimensional material between two isolation layers. - Source/drain regions are formed on the two-dimensional material. - Sacrificial layers are then removed to create spaces. - A gate stack is formed in the spaces. - The innovation allows for the creation of a structure with improved performance and functionality.

Abstract

A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

MULTIGATE DEVICE WITH AIR GAP SPACER AND BACKSIDE RAIL CONTACT AND METHOD OF FABRICATING THEREOF (18446151)

Main Inventor

Guan-Lin CHEN

Brief explanation

The patent application describes methods and devices involving a multigate device with specific components and features. 

• The device includes a channel layer located between a source feature and a drain feature.
• A metal gate surrounds the channel layer.
• A first air gap spacer is positioned between the metal gate and the source feature.
• A second air gap spacer is positioned between the metal gate and the drain feature.
• A backside contact extends to the source feature.
• A power line metallization layer is connected to the backside contact.

Abstract

Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME (17825411)

Main Inventor

Shin-Yi YANG

SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF (18447183)

Main Inventor

Chih-Ching Wang

SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF (17804125)

Main Inventor

Wen-Shun LO

Spacer Structures for Nano-Sheet-Based Devices (18446733)

Main Inventor

Shih-Cheng Chen

PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT (18447685)

Main Inventor

Anhao CHENG

Brief explanation

The patent application describes a semiconductor structure that includes a substrate with two active regions.

• The first active region is located in one part of the substrate, while the second active region is located in another part.
• The structure includes multiple gate structures over each active region.
• Each gate structure consists of a gate stack with a high-k gate dielectric, a gate electrode, and gate spacers.
• The gate structures over the second active region also contain dopants in a portion of the gate electrode.
• The purpose of this structure is not explicitly mentioned in the abstract.

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

Gate Spacers In Semiconductor Devices (18232191)

Main Inventor

Wei-Liang LU

Brief explanation

The patent application describes a semiconductor device and methods for making it.

• The device includes a substrate, a fin structure, a source/drain region, a gate structure, and a gate spacer.
• The fin structure is located on the substrate and has a fin top surface.
• The source/drain region is located on the fin structure.
• The gate structure is located on the fin top surface.
• The gate spacer has two portions: a first portion above the fin top surface and along the gate structure's sidewall, and a second portion below the fin top surface and along the source/drain region's sidewall.

Abstract

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

METHODS OF FORMING GATE STRUCTURES WITH UNIFORM GATE LENGTH (18446958)

Main Inventor

Shahaji B. More

Brief explanation

The patent application describes a device with two gate regions and spacers on their sidewalls.

• The first gate region has a certain length, and a spacer is placed on its sidewall.
• A semiconductor layer is placed over the first gate region.
• The second gate region is placed over the semiconductor layer, with the same length as the first gate region.
• A wider spacer is placed on the sidewall of the second gate region.

Abstract

A device includes a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate region over the semiconductor layer, wherein the second gate region has a second gate length equal to the first gate length; and a second spacer on a sidewall of second gate region, wherein the second spacer is wider than the first spacer.

Semiconductor Device with Air-Spacer (18446190)

Main Inventor

Wei-Yang Lee

Brief explanation

The patent application describes a semiconductor device with specific features and materials used in its construction. Here is a simplified explanation of the abstract:

• The semiconductor device consists of a substrate, two source/drain regions, and a gate stack.
• A spacer layer covers the sidewalls of the gate stack, and an S/D contact metal is placed over one of the source/drain regions.
• A first dielectric layer covers the sidewalls of the S/D contact metal, and an inter-layer dielectric (ILD) layer covers the first dielectric layer, spacer layer, and gate stack.
• The ILD layer creates a gap, and the material of one sidewall of the gap is different from the materials of the top and bottom surfaces of the gap.
• Similarly, the material of the other sidewall of the gap is also different from the materials of the top and bottom surfaces of the gap.

Bullet points to explain the patent/innovation:

• The semiconductor device includes specific components such as a substrate, source/drain regions, gate stack, spacer layer, S/D contact metal, and dielectric layers.
• The use of different materials in the sidewalls of the gap helps optimize the performance and functionality of the device.
• This innovation may improve the electrical properties, thermal characteristics, or other aspects of the semiconductor device.
• The specific materials used in the sidewalls of the gap may be chosen based on their unique properties and compatibility with the overall device structure.
• The patent application aims to protect the novel design and construction of the semiconductor device, which may have potential applications in various electronic devices and systems.

Abstract

A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

3D CAPACITOR AND METHOD OF MANUFACTURING SAME (18366596)

Main Inventor

Chi-Wen LIU

GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE (17824690)

Main Inventor

Tien-Shun CHANG

SELF-ALIGNED INNER SPACER ON GATE-ALL-AROUND STRUCTURE AND METHODS OF FORMING THE SAME (18359597)

Main Inventor

Tsungyu Hung

Brief explanation

- The patent application describes a semiconductor device and a method for manufacturing it.

- The method involves forming a fin structure on a substrate, consisting of two semiconductor layers with different materials, and including a channel region and a source/drain region. - A dummy gate structure is then formed over the substrate and fin. - A portion of the fin in the source/drain region is etched. - The edge portion of the second semiconductor layer in the channel region is selectively removed, causing it to be recessed, while the edge portion of the first semiconductor layer is suspended. - A reflow process is performed on the first semiconductor layer, creating an inner spacer that forms sidewall surfaces of the source/drain region. - Finally, a source/drain feature is epitaxially grown in the source/drain region.

Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

TRANSISTOR ISOLATION STRUCTURES (18446674)

Main Inventor

Mrunal Abhijith KHADERBAD

Brief explanation

The patent application describes a method for creating spacer structures in nanostructure transistors. 

• The method involves forming a fin structure with alternating nanostructure elements on a substrate.
• The edge portions of the nanostructure elements are etched to create spacer cavities.
• A spacer layer is then deposited to fill the spacer cavities.
• The spacer layer is treated with a microwave-generated plasma to create an oxygen concentration gradient within the layer.
• The treated portion of the spacer layer is removed using an etching process, with the removal rate based on the oxygen concentration gradient.

Abstract

The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF (18446632)

Main Inventor

Chih-Hsuan Lin

Brief explanation

- The patent application describes a semiconductor structure and a method for manufacturing it.

- The structure includes various components such as a substrate, conductive region, insulation layers, gate structure, low-k spacer, gate contact, and conductive region contact. - The low-k spacer is positioned between the sidewall of the gate structure and the first insulation layer. - The gate contact is placed on the top surface of the gate structure. - The proximity distance between the sidewall of the gate contact and the conductive region contact on the top surface of the second insulation layer is between approximately 4 nm and 7 nm. - The method for manufacturing the semiconductor structure is also explained in the patent application.

Abstract

A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.

CIRCUIT DEVICES WITH GATE SEALS (18447467)

Main Inventor

Sheng-Chou Lai

Brief explanation

- The patent application describes a circuit device that includes gate stacks and gate seals.

- The device is made by receiving a substrate with a fin extending from it. - A placeholder gate is formed on the fin, and first and second gate seals are formed on the sides of the placeholder gate. - The placeholder gate is then selectively removed, creating a recess between the side surfaces of the first and second gate seals. - A functional gate is then formed within the recess, between the side surfaces of the first and second gate seals.

• The circuit device includes gate stacks and gate seals.
• A placeholder gate is formed on a fin extending from a substrate.
• First and second gate seals are formed on the sides of the placeholder gate.
• The placeholder gate is selectively removed, creating a recess between the gate seals.
• A functional gate is formed within the recess, between the gate seals.

Abstract

Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.

TRANSISTOR SPACER STRUCTURES (18447680)

Main Inventor

Chansyun David YANG

Brief explanation

- The patent application describes a method for reducing parasitic capacitance between a transistor's gate structures and the source/drain contacts.

- The method involves forming a gate structure on a substrate and a spacer stack on the sidewall surfaces of the gate structure. - The spacer stack includes an inner spacer layer, a sacrificial spacer layer, and an outer spacer layer. - The sacrificial spacer layer is removed to create an opening between the inner and outer spacer layers. - A polymer material is deposited on the top surfaces of the inner and outer spacer layers. - The top sidewall surfaces of the inner and outer spacer layers are etched to create a tapered top portion. - A seal material is then deposited. - The resulting gate spacer structures with air-gaps help reduce parasitic capacitance.

Abstract

The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure—where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.

Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof (18446998)

Main Inventor

Chun-An Lin

Brief explanation

The patent application describes techniques for forming source and drain regions in FinFETs to reduce channel resistance and drain-induced barrier lowering (DIBL).

• The method involves a three-step etch process to create a recess in the source/drain region of a fin.
• The first anisotropic etch and isotropic etch are adjusted to determine the location of the source/drain tip.
• The depth of the recess after the first etches is less than the desired depth.
• The second anisotropic etch is then used to extend the depth of the recess to the target depth.
• The source/drain tip is positioned near the top of the fin to minimize channel resistance.
• The bottom portion of the recess is spaced away from the gate footing to reduce DIBL.
• The recess is filled with an epitaxial semiconductor material.

Abstract

Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17826174)

Main Inventor

Wang-Chun Huang

Channel Structures For Semiconductor Devices (18232159)

Main Inventor

Ding-Kang SHIH

Brief explanation

The present disclosure relates to channel structures of a semiconductor device and methods for fabricating them. 

• The method involves forming a superlattice structure with first and second nanostructured layers on a fin structure.
• The second nanostructured layers are then removed to create multiple gate openings.
• A germanium epitaxial growth layer is formed on the first nanostructured layers at a specific temperature and pressure.
• The temperature and pressure are then increased over a predetermined period of time.
• The germanium epitaxial growth layer is annealed at the increased temperature and pressure to form a cladding layer around the first nanostructured layers.

Abstract

The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

Controlling Fin-Thinning Through Feedback (18361540)

Main Inventor

Tsu-Hui Su

Brief explanation

The patent application describes a method for forming isolation regions in a semiconductor substrate and creating a semiconductor fin.

• Isolation regions are formed in the semiconductor substrate.
• A semiconductor strip is placed between the isolation regions.
• The isolation regions are recessed, allowing the semiconductor strip to protrude higher and form a semiconductor fin.
• The fin width of the semiconductor fin is measured.
• An etch recipe is generated based on the measured fin width.
• A thinning process is performed on the semiconductor fin using the etching recipe.

Abstract

A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Liner for A Bi-Layer Gate Helmet and the Fabrication Thereof (18365315)

Main Inventor

Huan-Chieh Su

Brief explanation

The patent application describes a semiconductor device with a unique structure and composition. Here are the key points:

• The device includes a semiconductor layer.
• A gate structure is placed on top of the semiconductor layer.
• A spacer is positioned on the side of the gate structure.
• The spacer is taller than the gate structure.
• A liner is applied to both the gate structure and the spacer.
• The spacer and the liner are made of different materials.

Overall, this patent application introduces a novel design for a semiconductor device, utilizing a taller spacer and different material compositions for the spacer and liner.

Abstract

A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same (18366297)

Main Inventor

Tzu-Chung Wang

Brief explanation

- The patent application describes techniques for creating a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device.

- The semiconductor structure includes a substrate and multiple separate semiconductor nanowire strips stacked vertically over the substrate. - A semiconductor epitaxy region is adjacent to and laterally contacts each of the nanowire strips. - A gate structure is positioned at least partially over the nanowire strips. - A dielectric structure is positioned laterally between the semiconductor epitaxy region and the gate structure. - The dielectric structure has a hat-shaped profile. - The innovation aims to improve the performance and efficiency of gate-all-around FET devices by creating a low resistance junction between the source/drain region and the nanowire channel region. - The hat-shaped profile of the dielectric structure helps in achieving this low resistance junction.

Abstract

The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

STRUCTURE FOR REDUCING SOURCE/DRAIN CONTACT RESISTANCE AT WAFER BACKSIDE (18366370)

Main Inventor

Huan-Chieh Su

Brief explanation

The patent application describes a semiconductor structure with specific features and connections.

• The structure includes a power rail and an isolation structure above it.
• There are two source/drain (S/D) features over the isolation structure, connected by one or more channel layers.
• A via structure connects one of the S/D features to the power rail, while a dielectric feature physically contacts the other S/D feature and the power rail.
• The via structure has a larger width in a cross-section perpendicular to the direction between the S/D features, compared to the width of the dielectric feature in a cross-section parallel to the first one.

Abstract

A semiconductor structure includes a power rail; an isolation structure over the power rail; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature; one or more channel layers over the isolation structure and connecting the first and the second S/D features; a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail. The first via structure has a first width in a first cross-section perpendicular to the first direction, the first dielectric feature has a second width in a second cross-section parallel to the first cross-section, and the first width is greater than the second width.

SEMICONDUCTOR DEVICE AND METHOD (18446905)

Main Inventor

Shahaji B. More

Brief explanation

The patent application describes methods for creating a multi-layer structure with controlled diffusion interfaces between different semiconductor materials. 

• The process involves depositing semiconductor layers at low temperatures to manage the inter-diffusion rate between the materials, resulting in abrupt Si/SiGe interfaces.
• The controlled interfaces and layers improve etching selectivity in the multi-layer structure.
• The invention is particularly useful for forming gate all-around (GAA) transistors with horizontal nanowires (NWs).
• The GAA transistors can be created with horizontal NWs of the same size diameters and SiGe NWs with "all-in-one" Si caps.

Abstract

Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.

Isolation Structures Of Semiconductor Devices (18447953)

Main Inventor

Jia-Chuan You

Brief explanation

- The patent application describes a semiconductor structure and a method for forming it.

- The structure includes a substrate, a first vertical structure, and a second vertical structure formed over the substrate. - An isolation structure is present between the first and second vertical structures. - The isolation structure consists of a center region and footing regions on opposite sides of the center region. - The footing regions are tapered towards the center region from one end to the other. - The purpose of the invention is to provide an improved semiconductor structure with enhanced isolation capabilities.

Abstract

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

EPITAXIAL STRUCTURES FOR FIN-LIKE FIELD EFFECT TRANSISTORS (18359542)

Main Inventor

Chia-Ta Yu

Brief explanation

The patent application describes a semiconductor structure with two fins protruding from a substrate, separated by isolation features.

• The top surface of each fin is lower than the top surface of the isolation features.
• Inner fin spacers are placed along the inner sidewalls of the fins, with a certain height measured from the top surface of the isolation features.
• Outer fin spacers are placed along the outer sidewalls of the fins, with a lower height measured from the top surface of the isolation features compared to the inner fin spacers.
• A source/drain structure merges the two fins and includes an air gap over the inner fin spacers.

Abstract

A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE (18232289)

Main Inventor

Chia-Chi YU

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18232544)

Main Inventor

Shih-Yao LIN

SYSTEM AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES (18446738)

Main Inventor

Chia-Ao Chang

Brief explanation

The patent application describes a method of manufacturing semiconductor devices.

• A recess is formed between fins in a substrate.
• A dielectric layer is formed over the fins and in the recess.
• A bottom seed structure is formed over the dielectric layer within the recess.
• The dielectric layer is exposed along the sidewalls of the recess.
• A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process.
• The dummy gate material is not grown from the dielectric layer exposed along the sidewalls of the recess.

Abstract

A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447489)

Main Inventor

Wei-Chih KAO

Method of Gap Filling for Semiconductor Device (18447618)

Main Inventor

Te-Yang Lai

Brief explanation

The patent application describes a method of manufacturing a semiconductor device.

• The method involves forming a dielectric layer over a plurality of fins on a substrate.
• A first high-k layer is then formed over the dielectric layer.
• A flowable oxide is formed, filling trenches adjacent to the fins.
• The flowable oxide is recessed to create trenches between the fins.
• A second high-k layer is formed over the first high-k layer and the flowable oxide.
• Planarization is performed to expose the top surfaces of the fins.
• The dielectric layer is recessed to create dummy fins, which include remaining portions of the high-k layers and the flowable oxide.

Abstract

A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

GATED METAL-INSULATOR-SEMICONDUCTOR (MIS) TUNNEL DIODE HAVING NEGATIVE TRANSCONDUCTANCE (18361758)

Main Inventor

Jenn-Gwo Hwu

Brief explanation

The patent application describes gated MIS tunnel diode devices with controllable negative transconductance behavior.

• The device includes a substrate, a tunnel diode dielectric layer, and a gate dielectric layer.
• A tunnel diode electrode and a gate electrode are positioned on the respective dielectric layers.
• A substrate electrode is also present on the substrate surface.
• The tunnel diode electrode is located between the gate electrode and the substrate electrode.
• The device allows for control over the negative transconductance behavior.

Abstract

Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE (18364679)

Main Inventor

Man-Ho Kwan

FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME (17827755)

Main Inventor

Gerben Doornbos

SEMICONDUCTOR DEVICE AND METHOD (18447153)

Main Inventor

Bo-Feng Young

Brief explanation

The patent application describes a semiconductor device and manufacturing method that uses metallic seeds to crystallize a ferroelectric layer.

• A metal layer and a ferroelectric layer are formed next to each other in the device.
• The metal layer is diffused into the ferroelectric layer.
• A crystallization process is then performed using the metal layer as seed crystals.
• This method helps to improve the crystallization of the ferroelectric layer in the semiconductor device.

Abstract

A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.

DEVICES WITH STRAINED ISOLATION FEATURES (18446960)

Main Inventor

Xusheng Wu

Brief explanation

The abstract describes a semiconductor device and a method of forming it.

• The semiconductor device includes two fins, each with a source/drain region.
• There is an isolation layer between the two source/drain regions.
• A second isolation layer is placed on top of the first isolation layer.
• The first isolation layer is present on the sidewalls of the source/drain regions.
• The second isolation layer is positioned between the first isolation layer on the sidewalls.

Abstract

A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES (18447483)

Main Inventor

Chih-Ching Wang

Brief explanation

The patent application describes a method for manufacturing a semiconductor substrate with a fin structure. Here are the key points:

• The method starts with receiving a semiconductor substrate with a fin structure on its top surface.
• The fin structure is recessed to create source/drain trenches.
• A first dielectric layer is formed over the recessed fin structure in the trenches.
• A dopant element is implanted into a portion of the fin structure beneath the trenches to create an amorphous semiconductor layer.
• A second dielectric layer is formed over the recessed fin structure in the trenches.
• The semiconductor substrate is annealed to enhance its properties.
• The first and second dielectric layers are removed.
• The recessed fin structure is further recessed to provide a top surface.
• An epitaxial layer is formed on the top surface of the fin structure.

Overall, the method involves creating source/drain trenches, implanting a dopant, and forming dielectric layers before annealing and removing the layers. Finally, the fin structure is further recessed and an epitaxial layer is formed on top.

Abstract

A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES (18227712)

Main Inventor

Cheng-Yi PENG

Brief explanation

The patent application describes a semiconductor device structure and a method of fabricating it.

• The semiconductor device includes a substrate, nanostructured layers, and source/drain (S/D) regions.
• The S/D regions have an epitaxial region wrapped around the nanostructured regions.
• The device also includes a gate-all-around (GAA) structure wrapped around the nanostructured regions.
• Inner spacers are placed between the S/D regions and the GAA structure.
• A passivation layer is applied to the sidewalls of the nanostructured regions.
• The innovation improves the performance and efficiency of the semiconductor device.

Abstract

The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions

METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE (18446539)

Main Inventor

Eric PENG

SEMICONDUCTOR DEVICE WITH SELF-ALIGNED WAVY CONTACT PROFILE AND METHOD OF FORMING THE SAME (18447855)

Main Inventor

Chia-Ta Yu

Brief explanation

The patent application describes a semiconductor device and a method of manufacturing it.

• The semiconductor device includes a fin structure on a substrate, a gate structure, and a source/drain feature.
• The fin structure has a channel region and a source/drain region.
• The gate structure is positioned over the channel region of the fin structure.
• The source/drain feature is grown epitaxially in the source/drain region of the fin structure.
• The source/drain feature consists of a top epitaxial layer and a lower epitaxial layer.
• The lower epitaxial layer has a wavy top surface.
• The contact of the semiconductor device has a wavy bottom surface that matches the wavy top surface of the lower epitaxial layer.
• The contact is engaged with the lower epitaxial layer of the source/drain feature.

Abstract

A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION (17804438)

Main Inventor

Jhu-Min SONG

Ferroelectric Semiconductor Device and Method (18447453)

Main Inventor

Chia-Cheng Ho

Brief explanation

The patent application describes a method for creating a ferroelectric semiconductor device.

• The method involves using a diffusion anneal process to drive dopant elements through a silicon layer and into a gate dielectric layer.
• This forms a doped gate dielectric layer with a gradient depth profile of dopant concentrations.
• The doped gate dielectric layer is then crystallized during a post-cap anneal process.
• This creates a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer.
• A metal gate electrode is then formed over the crystallized gate dielectric layer.
• This results in a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel.
• The ferroelectric transistor can be used in deep neural network applications.

Abstract

A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) appl

ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS (18446664)

Main Inventor

Shi Ning Ju

SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE (17824669)

Main Inventor

Hung-Yu YEN

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (17825516)

Main Inventor

Shuen-Shin LIANG

Semiconductor Device With Fish Bone Structure And Methods Of Forming The Same (18359280)

Main Inventor

Chih-Chuan Yang

Brief explanation

The patent application describes a semiconductor device and its manufacturing method.

• The device includes two semiconductor stacks made up of stacked and separated semiconductor layers.
• A dummy spacer is placed between the two semiconductor stacks, contacting the sidewalls of each semiconductor layer.
• A gate structure wraps around the second sidewall, top surface, and bottom surface of each semiconductor layer in the stacks.

Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18359690)

Main Inventor

Marcus Johannes Henricus VAN DAL

SEMICONDUCTOR DEVICE AND METHOD (18446918)

Main Inventor

Chunchieh Wang

Brief explanation

The patent application describes a device with nanostructures on a substrate, including a first set and a second set of nanostructures, each with a channel region. 

• The device also includes a gate dielectric layer that wraps around both sets of nanostructures.
• A first work function tuning layer is placed on the gate dielectric layer of the first set of nanostructures, wrapping around each of them.
• A glue layer is then added on top of the first work function tuning layer, also wrapping around each of the first set of nanostructures.
• A second work function tuning layer is applied on top of the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures.
• Finally, a fill layer is added on top of the second work function tuning layer.

Abstract

An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer.

METHOD OF MAKING DECOUPLING CAPACITOR (18447194)

Main Inventor

Szu-Lin LIU

SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS (17827251)

Main Inventor

Po-Chia Lai

DECOUPLING FINFET CAPACITORS (18358464)

Main Inventor

Chung-Hui Chen

VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING (18446031)

Main Inventor

Chin-Ho Chang

CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME (18362916)

Main Inventor

Seid Hadi RASOULI

DATA RETENTION CIRCUIT AND METHOD (18363192)

Main Inventor

Kai-Chi HUANG

Flip Flop Circuit (18366981)

Main Inventor

Po-Chia Lai

SYSTEM AND SEMICONDUCTOR DEVICE THEREIN (17828834)

Main Inventor

Tsung-Che LU

POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION (17828581)

Main Inventor

Chin-Hua Wen

Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18446849)

Main Inventor

Jerrin Pathrose Vareed

Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18447372)

Main Inventor

Jerrin Pathrose Vareed

Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation (18446881)

Main Inventor

Tsung-Hsien Tsai

Programmable Regulator Voltage Controlled Ring Oscillator (18366742)

Main Inventor

Tsung-Hsien Tsai

Circuits and Methods for a Noise Shaping Analog To Digital Converter (18361949)

Main Inventor

Martin Kinyua

RADIO FREQUENCY SWITCH (18231772)

Main Inventor

Jun-De JIN

Brief explanation

The abstract describes a RF switch module and methods for its fabrication and operation.

• The RF switch module is designed to alternate between connecting an antenna to a transmitter transmission line or a receiver transmission line.
• The goal of the switch module is to reduce distortion of signals at high frequencies, improve insertion loss, and maintain isolation.
• The switch circuit in the module consists of multiple field effect transistors (FETs).
• Each FET in the switch circuit has stacked gate dielectrics and at least three metal contacts to a conductive gate.
• The stacked gate dielectrics include at least one layer of a negative-capacitance material.
• The use of negative-capacitance material in the first dielectric layer helps to achieve the desired improvements in signal quality.
• The disclosed invention provides a solution for effectively switching signals between a transmitter and receiver while maintaining signal integrity.

Abstract

Disclosed is a RF switch module and methods to fabricate and operate such RF switch to alternatively couple an antenna to either a transmitter transmission line or a receiver transmission line to realize lower distortion of a signal at high frequencies with improved insertion loss and without affecting isolation. In one embodiment, a Radio Frequency (RF) switch module, includes, a switch circuit for switching between transmitting first signals from a transmitter unit to an antenna and transmitting second signals from the antenna to the receiver unit, wherein the switch circuit comprises a plurality of field effect transistors (FETs), wherein each of the plurality of FETs comprises stacked gate dielectrics and at least three metal contacts to a conductive gate, wherein the stacked gate dielectrics comprises at least one first dielectric layer, wherein the first dielectric layer comprises a negative-capacitance material.

METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE (18361816)

Main Inventor

En-Hsiang YEH

METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS (18232336)

Main Inventor

Shih-Lien Linus LU

Brief explanation

The patent application describes a physical unclonable function (PUF) generator circuit and testing method.

• The PUF generator includes a PUF cell array with multiple bit cells arranged in columns and rows.
• Each column is connected to at least two pre-discharge transistors, and each bit cell has enable transistors, access transistors, and storage nodes.
• A PUF control circuit is connected to the PUF cell array and is responsible for pre-charging the storage nodes with the same voltages to establish a first logical state.
• The control circuit then determines a second logical state based on the voltages of the storage nodes in each bit cell.
• Using the determined second logical states, the control circuit generates a PUF signature.

Abstract

Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.

EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY (18231017)

Main Inventor

Shang-Chieh CHIEN

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17826225)

Main Inventor

Chun-Hung CHEN

IC INCLUDING STANDARD CELLS AND SRAM CELLS (18361185)

Main Inventor

Jhon-Jhy LIAW

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446094)

Main Inventor

Shih-Yao Lin

STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT (18446546)

Main Inventor

Po-Sheng WANG

Brief explanation

The patent application describes a memory device with a pre-charge circuit.

• The memory device includes a memory cell and a pre-charge circuit.
• The pre-charge circuit consists of two transistors - a first transistor and a second transistor.
• The first transistor has a first gate terminal, a first source/drain terminal connected to a reference voltage, and a second source/drain terminal connected to one terminal of the memory cell.
• The second transistor has a second gate terminal, a third source/drain terminal connected to the reference voltage, and a fourth source/drain terminal connected to the other terminal of the memory cell.
• The first and second transistors are designed to allow the reference voltage to pass through when a control signal is applied to their respective gate terminals.

Abstract

The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.

MULTI-LAYER HIGH-K GATE DIELECTRIC STRUCTURE (18446593)

Main Inventor

Chih-Yu Hsu

Brief explanation

The patent application describes a transistor with a gate structure consisting of two layers of dielectric material.

• The first layer, called the first gate dielectric layer, is placed on top of the substrate and contains a dielectric material with a certain dielectric constant.
• The second layer, called the second gate dielectric layer, is placed on top of the first layer and contains a different dielectric material with a higher dielectric constant.
• Both dielectric materials have a higher dielectric constant than silicon oxide, which is commonly used in transistors.
• The use of these two layers with different dielectric constants in the gate structure of the transistor is the innovation described in the patent application.

Abstract

A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17828123)

Main Inventor

Jhon-Jhy LIAW

MEMORY DEVICES AND METHODS FOR OPERATING THE SAME (17752580)

Main Inventor

Hsiang-Wei Liu

MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT (18447638)

Main Inventor

Meng-Sheng CHANG

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361249)

Main Inventor

Meng-Han Lin

Polysilicon Removal In Word Line Contact Region Of Memory Devices (18447965)

Main Inventor

Yen-Jou WU

Brief explanation

The abstract describes a process for removing material between polysilicon lines in a memory cell strap region. 

• The process involves depositing a first hard mask layer in a divot on top of a polysilicon layer between two polysilicon gates.
• A second hard mask layer is then deposited on top of the first hard mask layer.
• A first etch is performed to remove the second hard mask layer and a portion of the first hard mask layer from the divot.
• A second etch is performed to remove the remaining second hard mask layer from the divot.
• Finally, a third etch is performed to remove the polysilicon layer not covered by the hard mask layers, creating a separation between the two polysilicon gates.

Abstract

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18446582)

Main Inventor

Feng-Ching Chu

FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME (18181229)

Main Inventor

Yi-Hsuan Chen

MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361548)

Main Inventor

Meng-Han Lin

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD (18366740)

Main Inventor

Chia-Yu Ling

Brief explanation

- The patent application describes a method for manufacturing 3D memory array devices.

- The method involves etching two trenches in a multilayer stack, which consists of alternating dielectric layers and sacrificial layers. - A word line is formed by replacing a sacrificial layer with a conductive material. - A first transistor is formed in the first trench, which includes a first channel isolation structure. - A cut channel plug is formed in the second trench, aligned with the channel isolation structure. - A second transistor is formed adjacent to the cut channel plug in the second trench. - The word line is electrically connected to both the first and second transistors.

Abstract

3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18446894)

Main Inventor

Meng-Han Lin

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18358966)

Main Inventor

Gerben Doornbos

Memory Array and Methods of Forming Same (18365068)

Main Inventor

Yu-Ming Lin

Brief explanation

The patent application describes a device that includes a semiconductor substrate and multiple word lines and gate electrodes for transistors.

• The device has a first word line that provides a gate electrode for a first transistor and a second word line that provides a gate electrode for a second transistor.
• The second word line is insulated from the first word line by a dielectric material.
• The device also includes a source line and a bit line that intersect with the word lines.
• A memory film is located between the first word line and the source line.
• A first semiconductor material is present between the memory film and the source line.

Abstract

A device includes a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, and the second word line providing a second gate electrode for a second transistor over the first transistor. The device further including a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a memory film between the first word line and the source line; and a first semiconductor material between the memory film and the source line.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447495)

Main Inventor

Meng-Han Lin

Brief explanation

The patent application describes a method of manufacturing semiconductor devices with a ferroelectric random access memory (FRAM) array.

• The FRAM array is formed with bit line drivers and source line drivers located below it.
• The method includes the formation of a through via, which is created using the same processes used to form individual memory cells within the FRAM array.

Abstract

Semiconductor devices and methods of manufacture are provided wherein a ferroelectric random access memory array is formed with bit line drivers and source line drivers formed below the ferroelectric random access memory array. A through via is formed using the same processes as the processes used to form individual memory cells within the ferroelectric random access memory array.

MEMORY CELL ISOLATION (17826100)

Main Inventor

Tzu-Yu Chen

EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR (18446557)

Main Inventor

Kuan-Liang Liu

Memory Device and Methods of Forming Same (18446586)

Main Inventor

Chenchen Jacob Wang

Brief explanation

The patent application describes a semiconductor device that includes a memory cell in a memory array.

• The memory cell consists of two access transistors, each with a bottom electrode, a conductive gate, a channel region, and a top electrode.
• The access transistors are located in a first dielectric layer over a substrate.
• The conductive gate is in a second dielectric layer, which is positioned over the bottom electrode and the first dielectric layer.
• The channel region extends through the conductive gate to make contact with the bottom electrode.
• The top electrode is placed over the channel region.
• The described device aims to improve the functionality and performance of memory cells in semiconductor devices.

Abstract

In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE (17825440)

Main Inventor

Wei-Chih WEN

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE (18448100)

Main Inventor

Yu-Hao CHEN

SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION (18232027)

Main Inventor

Yi Yang

Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices (18361677)

Main Inventor

Yi Yang

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME (18361832)

Main Inventor

Hsiang-Ku Shen

Brief explanation

The patent application describes a semiconductor device that includes various components such as a substrate, metal line, dielectric layer, bottom electrode via, bottom electrode, magnetic tunneling junction stack, and top electrode.

• The device has a substrate with a metal line embedded in it.
• A dielectric layer is placed on top of the substrate.
• A bottom electrode via extends through the dielectric layer and connects to the metal line.
• A bottom electrode is placed on top of the bottom electrode via.
• A magnetic tunneling junction stack is placed on top of the bottom electrode.
• A top electrode is placed on top of the magnetic tunneling junction stack.
• The bottom electrode via is made up of two different metals - a first metal in the lower portion and a second metal in the upper portion.

Abstract

A semiconductor device includes a substrate with a metal line embedded in the substrate, a dielectric layer disposed on the substrate, a bottom electrode via extending through the dielectric layer and landing on a top surface of the metal line, a bottom electrode disposed on a top surface of the bottom electrode via, a magnetic tunneling junction stack disposed on a top surface of the bottom electrode, and a top electrode disposed on the magnetic tunneling junction stack. A lower portion of the bottom electrode via includes a first metal, and an upper portion of the bottom electrode via includes a second metal that is different from the first metal.

MRAM Fabrication and Device (18447383)

Main Inventor

Jung-Tang Wu

Brief explanation

The abstract describes a patent application related to a magnetoresistive random access memory (MRAM) device.

• The patent application proposes using a film of titanium nitride with a (111) crystal structure as the top electrode of the MRAM device.
• This is a departure from the conventional use of tantalum, tantalum nitride, or a multilayer of tantalum and tantalum nitride as the top electrode material.
• The use of titanium nitride with a (111) crystal structure aims to improve the performance and efficiency of the MRAM device.
• The patent application suggests that this new configuration can enhance the magnetic tunnel junction (MTJ) in the MRAM device.
• The proposed innovation may lead to advancements in MRAM technology, potentially enabling faster and more reliable data storage and retrieval.

Abstract

A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

MEMORY DEVICE AND METHOD OF FABRICATING THE SAME (17827998)

Main Inventor

Yen-Lin Huang

MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (17900892)

Main Inventor

Ming-Yuan Song

MEMORY DEVICE AND FABRICATION METHOD THEREOF (18446703)

Main Inventor

Jun-Yao CHEN

Brief explanation

The patent application describes a memory device with specific components and their arrangement. 

• The memory device consists of a bottom electrode, a magnetic tunnel junction (MTJ) stack, a top electrode, and a sidewall spacer.
• The MTJ stack is positioned above the bottom electrode.
• The top electrode is placed on top of the MTJ stack.
• The MTJ stack and the top electrode are surrounded laterally by a sidewall spacer.
• The outermost sidewall of the sidewall spacer is set back from the outermost sidewall of the bottom electrode.

Abstract

A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, a top electrode, and a sidewall spacer. The MTJ stack is over the bottom electrode. The top electrode is over the MTJ stack. The sidewall spacer laterally surrounds the MTJ stack and the top electrode. The sidewall spacer has an outermost sidewall laterally set back from an outermost sidewall of the bottom electrode.

SIDEWALL SPACER STRUCTURE FOR MEMORY CELL (18364697)

Main Inventor

Yao-Wen Chang

MAGNETIC TUNNEL JUNCTION STRUCTURES WITH PROTECTION OUTER LAYERS (18446398)

Main Inventor

Sheng-Chang CHEN

Brief explanation

The patent application is about a type of memory cell called magneto-resistive random access memory (MRAM) cell.

• The MRAM cell has an extended upper electrode.
• The patent application also describes a method of forming the MRAM cell.
• The MRAM cell includes a magnetic tunnel junction (MTJ) placed over a conductive lower electrode.
• Two protection layers are used to surround the sidewall of the MTJ.
• The two protection layers have different etch selectivity, meaning they can be selectively removed without affecting each other.

Abstract

The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. Two protection layers sequentially surround a sidewall of the MTJ. The two protection layers have etch selectivity over one another.

STRUCTURE AND METHOD FOR MRAM DEVICES (18446563)

Main Inventor

Tsung-Chieh Hsiao

MAGNETIC TUNNELING JUNCTION WITH SYNTHETIC FREE LAYER FOR SOT-MRAM (18447912)

Main Inventor

Chien-Min Lee

Brief explanation

The patent application describes a magnetic memory device that uses a spin-orbit torque induction spin Hall electrode and a synthetic anti-ferromagnetic structure.

• The device includes a free layer with a magnetic moment that is not aligned with the long axis of the magnetic tunnel junction (MTJ) stack or the direction of current flow through the spin Hall electrode.
• The MTJ stack generates an internal magnetic field to switch the state of the free layer.
• The free layer consists of a first layer and a second layer separated by a spacer layer, which may have the same or different crystalline structures.

Abstract

A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447232)

Main Inventor

Tung-Ying Lee

Brief explanation

The patent application describes a new method of manufacturing semiconductor devices with memory cells that have a double sided word line structure.

• The memory cells have two word lines, one on each side of the cells.
• The first word line is located on one side of the memory cells.
• The second word line is located on the opposite side of the memory cells.
• This double sided word line structure improves the performance and efficiency of the semiconductor devices.
• The method provides a more compact and cost-effective way of manufacturing memory cells.

Abstract

Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT (18358685)

Main Inventor

Hai-Dang TRINH

METHODS OF FORMING MEMORY DEVICES (18363751)

Main Inventor

Hung-Li Chiang