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| − | '''Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023'''
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| − | Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to the formation and structure of memory devices and semiconductor devices. These patents aim to improve the performance, functionality, and efficiency of these devices.
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| − | Summary:
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| − | - TSMC has filed patents for methods of forming memory devices, semiconductor devices, and magnetic memory devices.
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| − | - The methods involve the formation of specific layers, plugs, and structures to enhance the functionality and performance of the devices.
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| − | - The patents also describe the use of magnetic materials, spin-orbit torque induction structures, and magnetic tunnel junction stacks to improve the operation of the devices.
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| − | - TSMC's patents also include methods for etching magnetic tunneling junction structures and creating ultra-large height top electrodes for MRAM devices.
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| − | - The organization has also filed patents for semiconductor structures with optical components and thermal control mechanisms.
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| − | - Notable applications of these patents include data storage, magnetic sensors, and magnetoresistive random-access memory (MRAM) devices.
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| − | Bullet points:
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| − | * TSMC has filed patents for memory devices, semiconductor devices, and magnetic memory devices.
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| − | * The patents describe methods for forming specific layers, plugs, and structures to enhance device performance.
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| − | * Magnetic materials, spin-orbit torque induction structures, and magnetic tunnel junction stacks are used in the devices.
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| − | * Patents also cover methods for etching magnetic tunneling junction structures and creating large height top electrodes for MRAM devices.
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| − | * Semiconductor structures with optical components and thermal control mechanisms are also described.
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| − | * Applications include data storage, magnetic sensors, and MRAM devices.
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| | ==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023== | | ==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023== |
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| − | ===PARTICLE REMOVER AND METHOD ([[US Patent Application 18448963. PARTICLE REMOVER AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448963]])===
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| − | '''Main Inventor'''
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| − |
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| − | Wen-Hao Cheng
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| − |
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| − |
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| − | ===DEVICE FOR FORMING CONDUCTIVE POWDER ([[US Patent Application 18447161. DEVICE FOR FORMING CONDUCTIVE POWDER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447161]])===
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| − | '''Main Inventor'''
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| − |
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| − | You-Hua CHOU
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| − |
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| − |
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| − | ===POLISHING METROLOGY ([[US Patent Application 17898163. POLISHING METROLOGY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17898163]])===
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| − | '''Main Inventor'''
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| − |
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| − | Chih Hung CHEN
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| − |
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| − |
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| − | ===MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE ([[US Patent Application 18364702. MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364702]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Kuei-Sung Chang
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| − |
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| − |
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| − | ===MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE ([[US Patent Application 18446741. MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446741]])===
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| − | '''Main Inventor'''
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| − |
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| − | Chun-Wen Cheng
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| − |
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| − |
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| − | ===WIRE-BOND DAMPER FOR SHOCK ABSORPTION ([[US Patent Application 18446740. WIRE-BOND DAMPER FOR SHOCK ABSORPTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446740]])===
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| − | '''Main Inventor'''
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| − |
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| − | Tsung-Lin Hsieh
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| − |
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| − |
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| − | ===DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE ([[US Patent Application 17825225. DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825225]])===
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| − | '''Main Inventor'''
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| − |
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| − | Wen-Chuan Tai
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| − |
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| − |
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| − | ===SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL ([[US Patent Application 18447543. SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447543]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Yi-Lin WANG
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| − |
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| − |
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| − | ===TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS ([[US Patent Application 18150772. TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18150772]])===
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| − | '''Main Inventor'''
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| − |
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| − | Jaw-Juinn HORNG
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| − |
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| − |
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| − | ===TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS ([[US Patent Application 18170401. TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18170401]])===
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| − | '''Main Inventor'''
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| − |
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| − | Szu-Lin Liu
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| − |
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| − |
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| − | ===METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18362983. METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362983]])===
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| − | '''Main Inventor'''
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| − |
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| − | Feng-Wei KUO
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| − | ===FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME ([[US Patent Application 18448032. FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448032]])===
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| − | '''Main Inventor'''
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| − |
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| − | Chen-Hao HUANG
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| − |
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| − |
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| − | ===METHOD OF MAKING PHOTONIC DEVICE ([[US Patent Application 18448046. METHOD OF MAKING PHOTONIC DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448046]])===
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| − | '''Main Inventor'''
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| − |
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| − | Chien-Ying WU
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| − |
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| − |
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| − | ===METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING ([[US Patent Application 18448095. METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448095]])===
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| − | '''Main Inventor'''
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| − |
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| − | Sui-Ying HSU
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| − |
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| − |
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| − | ===METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING ([[US Patent Application 18358790. METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358790]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yu-Hao CHEN
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| − |
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| − |
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| − | ===PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF ([[US Patent Application 18232674. PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232674]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yun-Yue LIN
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| − |
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| − | ===PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME ([[US Patent Application 18362046. PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362046]])===
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| − | '''Main Inventor'''
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| − |
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| − | Kuo-Hao LEE
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| − |
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| − |
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| − | ===PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232264. PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232264]])===
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| − | '''Main Inventor'''
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| − |
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| − | An-Ren ZI
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| − |
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| − |
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| − | ===PHOTORESIST MATERIALS AND ASSOCIATED METHODS ([[US Patent Application 18447568. PHOTORESIST MATERIALS AND ASSOCIATED METHODS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447568]])===
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| − |
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Ming-Hui WENG
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| − |
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| − |
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| − | ===PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18232225. PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232225]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | An-Ren Zi
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| − |
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| − |
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| − | ===PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232220. PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232220]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yen-Hao CHEN
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| − |
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| − |
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| − | ===UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232774. UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232774]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Ming-Hui WENG
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| − |
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| − |
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| − | ===PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18232717. PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232717]])===
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| − | '''Main Inventor'''
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| − |
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| − | An-Ren ZI
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| − |
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| − | ===SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS ([[US Patent Application 18365529. SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365529]])===
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| − | '''Main Inventor'''
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| − |
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| − | Wen-Zhan Zhou
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| − |
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| − |
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| − | ===METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR ([[US Patent Application 18358904. METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358904]])===
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| − | '''Main Inventor'''
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| − | Hung-Jui Kuo
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| − | ===SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION ([[US Patent Application 18446870. SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446870]])===
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| − | '''Main Inventor'''
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| − | Kai-Chieh CHANG
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| − | ===OPTIMIZED MASK STITCHING ([[US Patent Application 18231070. OPTIMIZED MASK STITCHING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231070]])===
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| − | '''Main Inventor'''
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| − | Sagar TRIVEDI
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| − | ===ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18232745. ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232745]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yih-Chen SU
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| − | ===MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW ([[US Patent Application 18447361. MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447361]])===
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| − | '''Main Inventor'''
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| − |
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| − | Chun-Kai CHANG
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| − |
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| − |
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| − | ===SEMICONDUCTOR WAFER COOLING ([[US Patent Application 18362037. SEMICONDUCTOR WAFER COOLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362037]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yung-Yao LEE
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| − |
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| − | ===MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME ([[US Patent Application 18355222. MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18355222]])===
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| − | '''Main Inventor'''
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| − | Saman M. I. ADHAM
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| − | ===FAULT DIAGNOSTICS ([[US Patent Application 18303219. FAULT DIAGNOSTICS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18303219]])===
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| − | '''Main Inventor'''
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| − |
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| − | Sandeep Kumar Goel
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| − | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 17821559. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17821559]])===
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| − | '''Main Inventor'''
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| − |
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| − | Johnny Chiahao LI
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| − |
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| − | ===METHOD FOR CHIP INTEGRATION ([[US Patent Application 17828648. METHOD FOR CHIP INTEGRATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828648]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yung Feng Chang
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| − | ===SEMICONDUCTOR DEVICE ([[US Patent Application 18361815. SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361815]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yu-Jen CHEN
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| − |
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| − |
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| − | ===ANTI-FUSE ARRAY ([[US Patent Application 18446684. ANTI-FUSE ARRAY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446684]])===
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| − | '''Main Inventor'''
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| − |
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| − | Meng-Sheng CHANG
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| − |
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| − | ===INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 18446771. INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446771]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yu-Jung CHANG
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| − |
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| − |
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| − | ===METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS ([[US Patent Application 18447964. METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447964]])===
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| − | '''Main Inventor'''
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| − |
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| − | Yen-Pin CHEN
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| − |
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| − |
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| − | ===SILICON PHOTONICS SYSTEM ([[US Patent Application 18155980. SILICON PHOTONICS SYSTEM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18155980]])===
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| − |
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Feng-Wei KUO
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| − |
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| − |
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| − | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 18354377. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18354377]])===
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| − | '''Main Inventor'''
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| − |
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| − | John LIN
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| − |
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| − |
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| − | ===TRANSMISSION GATE STRUCTURE ([[US Patent Application 18362195. TRANSMISSION GATE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362195]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Shao-Lun CHIEN
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| − |
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| − |
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| − | ===SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT ([[US Patent Application 18448143. SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448143]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Fong-Yuan CHANG
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| − |
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| − |
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| − | ===NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY ([[US Patent Application 17824306. NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824306]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Chieh Lee
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| − |
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| − |
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| − | ===MEMORY DEVICE WITH SOURCE LINE CONTROL ([[US Patent Application 18232542. MEMORY DEVICE WITH SOURCE LINE CONTROL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232542]])===
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| − | '''Main Inventor'''
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| − |
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| − | Perng-Fei Yuh
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| − |
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| − | ===Systems and Methods for Controlling Power Management Operations in a Memory Device ([[US Patent Application 18446818. Systems and Methods for Controlling Power Management Operations in a Memory Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446818]])===
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| − | '''Main Inventor'''
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| − |
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| − | Sanjeev Kumar Jain
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| − |
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| − |
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| − | ===ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES ([[US Patent Application 18446072. ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446072]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Chien-Yuan Chen
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| − |
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| − |
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| − | ===FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR ([[US Patent Application 17826180. FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826180]])===
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| − | '''Main Inventor'''
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| − |
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| − | Elia Ambrosi
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| − |
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| − |
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| − | ===MEMORY DEVICE WITH REDUCED AREA ([[US Patent Application 17752662. MEMORY DEVICE WITH REDUCED AREA simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752662]])===
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| − |
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Chun-Ying Lee
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| − |
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| − |
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| − | ===THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY ([[US Patent Application 18232539. THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232539]])===
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| − |
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Meng-Sheng Chang
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| − |
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| − |
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| − | ===NON-VOLATILE MEMORY CIRCUIT AND METHOD ([[US Patent Application 18448152. NON-VOLATILE MEMORY CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448152]])===
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Gu-Huan LI
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| − |
| |
| − |
| |
| − | ===FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL ([[US Patent Application 18447410. FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447410]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Sheng-Chieh HUANG
| |
| − |
| |
| − |
| |
| − | ===DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING ([[US Patent Application 18231165. DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231165]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ming Che CHEN
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR TOOL FOR COPPER DEPOSITION ([[US Patent Application 18447557. SEMICONDUCTOR TOOL FOR COPPER DEPOSITION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447557]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chia-Hung TSAI
| |
| − |
| |
| − |
| |
| − | ===METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS ([[US Patent Application 18225576. METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18225576]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Wei-Lin CHANG
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE PRE-CLEANING ([[US Patent Application 17804447. SEMICONDUCTOR DEVICE PRE-CLEANING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804447]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yi-Hsiang CHAO
| |
| − |
| |
| − |
| |
| − | ===APPARATUS FOR ELECTRO-CHEMICAL PLATING ([[US Patent Application 18231196. APPARATUS FOR ELECTRO-CHEMICAL PLATING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231196]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Kuo-Lung HOU
| |
| − |
| |
| − |
| |
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 17829154. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17829154]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Po-Han LIN
| |
| − |
| |
| − |
| |
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18232758. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232758]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chun-Wei LIAO
| |
| − |
| |
| − |
| |
| − | ===METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL ([[US Patent Application 18447810. METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447810]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yun-Jui HE
| |
| − |
| |
| − |
| |
| − | ===NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL ([[US Patent Application 18446652. NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446652]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ya-Wen Chiu
| |
| − |
| |
| − |
| |
| − | ===CHEMICAL DISPENSING SYSTEM ([[US Patent Application 18447353. CHEMICAL DISPENSING SYSTEM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447353]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ming-Chieh HSU
| |
| − |
| |
| − |
| |
| − | ===SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE ([[US Patent Application 18358517. SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358517]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yi-Fam Shiu
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF ([[US Patent Application 18446549. SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446549]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Soon-Kang HUANG
| |
| − |
| |
| − |
| |
| − | ===ETCH METHOD FOR INTERCONNECT STRUCTURE ([[US Patent Application 18447134. ETCH METHOD FOR INTERCONNECT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447134]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chun-Cheng Chou
| |
| − |
| |
| − |
| |
| − | ===LOCAL INTERCONNECT ([[US Patent Application 18447549. LOCAL INTERCONNECT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447549]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Cheng-Hsien Wu
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME ([[US Patent Application 18230338. SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18230338]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ting-Ya LO
| |
| − |
| |
| − |
| |
| − | ===METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES ([[US Patent Application 17825307. METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825307]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yu-Chen KO
| |
| − |
| |
| − |
| |
| − | ===METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH ([[US Patent Application 17825678. METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825678]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chung-Liang CHENG
| |
| − |
| |
| − |
| |
| − | ===GATE CONTACT STRUCTURE ([[US Patent Application 18446326. GATE CONTACT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446326]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Cheng-Chi Chuang
| |
| − |
| |
| − |
| |
| − | ===METAL GATE PROCESS AND RELATED STRUCTURE ([[US Patent Application 17804146. METAL GATE PROCESS AND RELATED STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804146]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih-Lun LU
| |
| − |
| |
| − |
| |
| − | ===METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION ([[US Patent Application 18360814. METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360814]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Osamu KOIKE
| |
| − |
| |
| − |
| |
| − | ===METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE ([[US Patent Application 18361501. METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361501]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chung-Ting KO
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18447125. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447125]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shu-Uei Jang
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824249. SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824249]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ta-Chun LIN
| |
| − |
| |
| − |
| |
| − | ===REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES ([[US Patent Application 18359747. REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359747]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yu-Jen Shen
| |
| − |
| |
| − |
| |
| − | ===HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER ([[US Patent Application 18447239. HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447239]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Huiching Chang
| |
| − |
| |
| − |
| |
| − | ===METHOD FOR FORMING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824263. METHOD FOR FORMING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824263]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih-Hsin Yang
| |
| − |
| |
| − |
| |
| − | ===MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION ([[US Patent Application 18359206. MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359206]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | I-Che Lee
| |
| − |
| |
| − |
| |
| − | ===SYSTEMS AND METHODS OF TESTING MEMORY DEVICES ([[US Patent Application 18232518. SYSTEMS AND METHODS OF TESTING MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232518]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Meng-Han Lin
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE ([[US Patent Application 18232520. SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232520]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tsung-Yang Hsieh
| |
| − |
| |
| − |
| |
| − | ===MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE ([[US Patent Application 18363742. MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363742]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Meng-Liang Lin
| |
| − |
| |
| − |
| |
| − | ===STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE ([[US Patent Application 18446076. STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446076]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jen-Yuan CHANG
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING ([[US Patent Application 18447927. SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447927]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jian WU
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17827992. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827992]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Wei-Ming Wang
| |
| − |
| |
| − |
| |
| − | ===INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME ([[US Patent Application 17829243. INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17829243]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chang-Jung HSUEH
| |
| − |
| |
| − |
| |
| − | ===VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS ([[US Patent Application 17825336. VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825336]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ting-Yu Yeh
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18361917. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361917]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jen-Chun Liao
| |
| − |
| |
| − |
| |
| − | ===Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via ([[US Patent Application 18447871. Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447871]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yung-Chi Lin
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18359864. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359864]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ting-Yu Yeh
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH ([[US Patent Application 18232523. SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232523]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yueh-Ting Lin
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18363766. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363766]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chien-Hung Chen
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446873. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446873]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chung-Ting Lu
| |
| − |
| |
| − |
| |
| − | ===BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE ([[US Patent Application 18447722. BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447722]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tsung-Chieh Hsiao
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING ([[US Patent Application 17825698. SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825698]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih-Yu Lu
| |
| − |
| |
| − |
| |
| − | ===SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD ([[US Patent Application 17752704. SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752704]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chi-Yu LU
| |
| − |
| |
| − |
| |
| − | ===DIAGONAL VIA STRUCTURE ([[US Patent Application 18448125. DIAGONAL VIA STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448125]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shih-Wei PENG
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT ([[US Patent Application 18232306. SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232306]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Gerben DOORNBOS
| |
| − |
| |
| − |
| |
| − | ===ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY ([[US Patent Application 18446025. ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446025]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shih-Wei Peng
| |
| − |
| |
| − |
| |
| − | ===FIRST METAL STRUCTURE, LAYOUT, AND METHOD ([[US Patent Application 17752737. FIRST METAL STRUCTURE, LAYOUT, AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752737]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chi-Yu LU
| |
| − |
| |
| − |
| |
| − | ===POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS ([[US Patent Application 18361666. POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361666]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih-Liang CHEN
| |
| − |
| |
| − |
| |
| − | ===METHOD OF MANUFACTURING INTEGRATED CIRCUIT ([[US Patent Application 18447572. METHOD OF MANUFACTURING INTEGRATED CIRCUIT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447572]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih-Yu LAI
| |
| − |
| |
| − |
| |
| − | ===CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES ([[US Patent Application 18448005. CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448005]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Li-Chun Tien
| |
| − |
| |
| − |
| |
| − | ===METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS ([[US Patent Application 18448028. METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448028]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih-Liang CHEN
| |
| − |
| |
| − |
| |
| − | ===INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT ([[US Patent Application 18360012. INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360012]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shin-Yi Yang
| |
| − |
| |
| − |
| |
| − | ===INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS ([[US Patent Application 17825345. INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825345]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chien Hung Liu
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE ([[US Patent Application 17825741. SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825741]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Hsi-Wen TIEN
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF ([[US Patent Application 17823063. SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17823063]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Sheng-Fan YANG
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION ([[US Patent Application 17824353. SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824353]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shu-Chun Yang
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME ([[US Patent Application 18230999. SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18230999]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Cheng-Chieh HSIEH
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS ([[US Patent Application 17824330. SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824330]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Fong-yuan Chang
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18361953. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361953]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chung-Liang CHENG
| |
| − |
| |
| − |
| |
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME ([[US Patent Application 18447979. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447979]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Te-Hsin CHIU
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME ([[US Patent Application 17826604. SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826604]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yi-Ruei JHAN
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME ([[US Patent Application 18229682. SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18229682]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jui-Chien HUANG
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18362862. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362862]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yu-Lien HUANG
| |
| − |
| |
| − |
| |
| − | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 17828981. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828981]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chin-Wei HSU
| |
| − |
| |
| − |
| |
| − | ===LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE ([[US Patent Application 18366831. LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366831]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Harry-Hak-Lay Chuang
| |
| − |
| |
| − |
| |
| − | ===METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE ([[US Patent Application 18360214. METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360214]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ming Chyi Liu
| |
| − |
| |
| − |
| |
| − | ===IMAGE SENSOR WITH A HIGH ABSORPTION LAYER ([[US Patent Application 18364662. IMAGE SENSOR WITH A HIGH ABSORPTION LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364662]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chien-Chang Huang
| |
| − |
| |
| − |
| |
| − | ===PIXEL SENSOR INCLUDING A TRANSFER FINFET ([[US Patent Application 18447340. PIXEL SENSOR INCLUDING A TRANSFER FINFET simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447340]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Feng-Chien HSIEH
| |
| − |
| |
| − |
| |
| − | ===EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR ([[US Patent Application 18364667. EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364667]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shih-Hsun Hsu
| |
| − |
| |
| − |
| |
| − | ===IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION ([[US Patent Application 18446572. IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446572]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Hsiang-Lin Chen
| |
| − |
| |
| − |
| |
| − | ===METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY ([[US Patent Application 18360966. METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360966]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tsun-Kai Tsao
| |
| − |
| |
| − |
| |
| − | ===OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE ([[US Patent Application 17824183. OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824183]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yi-Hsien Chang
| |
| − |
| |
| − |
| |
| − | ===BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR ([[US Patent Application 18364682. BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364682]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Cheng-Ta Wu
| |
| − |
| |
| − |
| |
| − | ===DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR ([[US Patent Application 18364734. DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364734]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Feng-Chien HSIEH
| |
| − |
| |
| − |
| |
| − | ===INDUCTIVE DEVICE ([[US Patent Application 18447482. INDUCTIVE DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447482]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Wei-Yu CHOU
| |
| − |
| |
| − |
| |
| − | ===Resistor Structure ([[US Patent Application 18358557. Resistor Structure simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358557]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih-Fan Huang
| |
| − |
| |
| − |
| |
| − | ===A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE ([[US Patent Application 18366156. A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366156]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Szu-Hsien Lo
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17824436. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824436]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tsung-Chieh HSIAO
| |
| − |
| |
| − |
| |
| − | ===SUPER JUNCTION STRUCTURE ([[US Patent Application 18448013. SUPER JUNCTION STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448013]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shuai ZHANG
| |
| − |
| |
| − |
| |
| − | ===NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION ([[US Patent Application 18232545. NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232545]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Lin-Chen Lu
| |
| − |
| |
| − |
| |
| − | ===SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME ([[US Patent Application 18366210. SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366210]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ko-Cheng Liu
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17824329. SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824329]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Lin-Yu HUANG
| |
| − |
| |
| − |
| |
| − | ===GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME ([[US Patent Application 17804751. GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804751]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chi-Ming CHEN
| |
| − |
| |
| − |
| |
| − | ===EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION ([[US Patent Application 17824915. EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824915]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih Sheng Huang
| |
| − |
| |
| − |
| |
| − | ===INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE ([[US Patent Application 18363077. INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363077]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Hsin Fu Lin
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF ([[US Patent Application 17752211. SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752211]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jui-Lin CHANG
| |
| − |
| |
| − |
| |
| − | ===Semiconductor Gate-All-Around Device ([[US Patent Application 18360080. Semiconductor Gate-All-Around Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360080]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jhon Jhy Liaw
| |
| − |
| |
| − |
| |
| − | ===PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS ([[US Patent Application 18361262. PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361262]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Meng-Huan Jao
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER ([[US Patent Application 18446864. SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446864]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shih-Chuan Chiu
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF ([[US Patent Application 18360085. SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360085]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Po-Yu Huang
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION ([[US Patent Application 18447344. SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447344]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Te-Chih HSIUNG
| |
| − |
| |
| − |
| |
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES ([[US Patent Application 17752461. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752461]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yung-Hsiang CHAN
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME ([[US Patent Application 17825411. SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825411]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shin-Yi YANG
| |
| − |
| |
| − |
| |
| − | ===SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF ([[US Patent Application 18447183. SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447183]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chih-Ching Wang
| |
| − |
| |
| − |
| |
| − | ===SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF ([[US Patent Application 17804125. SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804125]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Wen-Shun LO
| |
| − |
| |
| − |
| |
| − | ===Spacer Structures for Nano-Sheet-Based Devices ([[US Patent Application 18446733. Spacer Structures for Nano-Sheet-Based Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446733]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shih-Cheng Chen
| |
| − |
| |
| − |
| |
| − | ===3D CAPACITOR AND METHOD OF MANUFACTURING SAME ([[US Patent Application 18366596. 3D CAPACITOR AND METHOD OF MANUFACTURING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366596]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chi-Wen LIU
| |
| − |
| |
| − |
| |
| − | ===GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE ([[US Patent Application 17824690. GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824690]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tien-Shun CHANG
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17826174. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826174]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Wang-Chun Huang
| |
| − |
| |
| − |
| |
| − | ===METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE ([[US Patent Application 18232289. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232289]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chia-Chi YU
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18232544. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232544]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shih-Yao LIN
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE ([[US Patent Application 18447489. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447489]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Wei-Chih KAO
| |
| − |
| |
| − |
| |
| − | ===INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE ([[US Patent Application 18364679. INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364679]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Man-Ho Kwan
| |
| − |
| |
| − |
| |
| − | ===FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME ([[US Patent Application 17827755. FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827755]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Gerben Doornbos
| |
| − |
| |
| − |
| |
| − | ===METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE ([[US Patent Application 18446539. METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446539]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Eric PENG
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| − |
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| − |
| |
| − | ===HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION ([[US Patent Application 17804438. HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804438]])===
| |
| − |
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Jhu-Min SONG
| |
| − |
| |
| − |
| |
| − | ===ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS ([[US Patent Application 18446664. ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446664]])===
| |
| − |
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| − |
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| − | '''Main Inventor'''
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| − |
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| − | Shi Ning Ju
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| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE ([[US Patent Application 17824669. SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824669]])===
| |
| − |
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| − |
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| − | '''Main Inventor'''
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| − |
| |
| − | Hung-Yu YEN
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| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17825516. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825516]])===
| |
| − |
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| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shuen-Shin LIANG
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 18359690. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359690]])===
| |
| − |
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| − |
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| − | '''Main Inventor'''
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| − |
| |
| − | Marcus Johannes Henricus VAN DAL
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| − |
| |
| − |
| |
| − | ===METHOD OF MAKING DECOUPLING CAPACITOR ([[US Patent Application 18447194. METHOD OF MAKING DECOUPLING CAPACITOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447194]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
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| − |
| |
| − | Szu-Lin LIU
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS ([[US Patent Application 17827251. SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827251]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Po-Chia Lai
| |
| − |
| |
| − |
| |
| − | ===DECOUPLING FINFET CAPACITORS ([[US Patent Application 18358464. DECOUPLING FINFET CAPACITORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358464]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chung-Hui Chen
| |
| − |
| |
| − |
| |
| − | ===VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING ([[US Patent Application 18446031. VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446031]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chin-Ho Chang
| |
| − |
| |
| − |
| |
| − | ===CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME ([[US Patent Application 18362916. CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362916]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Seid Hadi RASOULI
| |
| − |
| |
| − |
| |
| − | ===DATA RETENTION CIRCUIT AND METHOD ([[US Patent Application 18363192. DATA RETENTION CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363192]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Kai-Chi HUANG
| |
| − |
| |
| − |
| |
| − | ===Flip Flop Circuit ([[US Patent Application 18366981. Flip Flop Circuit simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366981]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Po-Chia Lai
| |
| − |
| |
| − |
| |
| − | ===SYSTEM AND SEMICONDUCTOR DEVICE THEREIN ([[US Patent Application 17828834. SYSTEM AND SEMICONDUCTOR DEVICE THEREIN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828834]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tsung-Che LU
| |
| − |
| |
| − |
| |
| − | ===POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION ([[US Patent Application 17828581. POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828581]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chin-Hua Wen
| |
| − |
| |
| − |
| |
| − | ===Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals ([[US Patent Application 18446849. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446849]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jerrin Pathrose Vareed
| |
| − |
| |
| − |
| |
| − | ===Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals ([[US Patent Application 18447372. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447372]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jerrin Pathrose Vareed
| |
| − |
| |
| − |
| |
| − | ===Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation ([[US Patent Application 18446881. Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446881]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tsung-Hsien Tsai
| |
| − |
| |
| − |
| |
| − | ===Programmable Regulator Voltage Controlled Ring Oscillator ([[US Patent Application 18366742. Programmable Regulator Voltage Controlled Ring Oscillator simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366742]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tsung-Hsien Tsai
| |
| − |
| |
| − |
| |
| − | ===Circuits and Methods for a Noise Shaping Analog To Digital Converter ([[US Patent Application 18361949. Circuits and Methods for a Noise Shaping Analog To Digital Converter simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361949]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Martin Kinyua
| |
| − |
| |
| − |
| |
| − | ===METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE ([[US Patent Application 18361816. METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361816]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | En-Hsiang YEH
| |
| − |
| |
| − |
| |
| − | ===EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY ([[US Patent Application 18231017. EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231017]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shang-Chieh CHIEN
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17826225. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826225]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Chun-Hung CHEN
| |
| − |
| |
| − |
| |
| − | ===IC INCLUDING STANDARD CELLS AND SRAM CELLS ([[US Patent Application 18361185. IC INCLUDING STANDARD CELLS AND SRAM CELLS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361185]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jhon-Jhy LIAW
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446094. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446094]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Shih-Yao Lin
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17828123. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828123]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Jhon-Jhy LIAW
| |
| − |
| |
| − |
| |
| − | ===MEMORY DEVICES AND METHODS FOR OPERATING THE SAME ([[US Patent Application 17752580. MEMORY DEVICES AND METHODS FOR OPERATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752580]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Hsiang-Wei Liu
| |
| − |
| |
| − |
| |
| − | ===MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT ([[US Patent Application 18447638. MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447638]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Meng-Sheng CHANG
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18361249. SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361249]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Meng-Han Lin
| |
| − |
| |
| − |
| |
| − | ===MEMORY DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18446582. MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446582]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Feng-Ching Chu
| |
| − |
| |
| − |
| |
| − | ===FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 18181229. FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18181229]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yi-Hsuan Chen
| |
| − |
| |
| − |
| |
| − | ===MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18361548. MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361548]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Meng-Han Lin
| |
| − |
| |
| − |
| |
| − | ===THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446894. THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446894]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Meng-Han Lin
| |
| − |
| |
| − |
| |
| − | ===SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME ([[US Patent Application 18358966. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358966]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Gerben Doornbos
| |
| − |
| |
| − |
| |
| − | ===MEMORY CELL ISOLATION ([[US Patent Application 17826100. MEMORY CELL ISOLATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826100]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tzu-Yu Chen
| |
| − |
| |
| − |
| |
| − | ===EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR ([[US Patent Application 18446557. EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446557]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Kuan-Liang Liu
| |
| − |
| |
| − |
| |
| − | ===METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 17825440. METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825440]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Wei-Chih WEN
| |
| − |
| |
| − |
| |
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18448100. METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448100]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yu-Hao CHEN
| |
| − |
| |
| − |
| |
| − | ===SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION ([[US Patent Application 18232027. SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232027]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yi Yang
| |
| − |
| |
| − |
| |
| − | ===Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices ([[US Patent Application 18361677. Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361677]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yi Yang
| |
| − |
| |
| − |
| |
| − | ===MEMORY DEVICE AND METHOD OF FABRICATING THE SAME ([[US Patent Application 17827998. MEMORY DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827998]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yen-Lin Huang
| |
| − |
| |
| − |
| |
| − | ===MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17900892. MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17900892]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Ming-Yuan Song
| |
| − |
| |
| − |
| |
| − | ===SIDEWALL SPACER STRUCTURE FOR MEMORY CELL ([[US Patent Application 18364697. SIDEWALL SPACER STRUCTURE FOR MEMORY CELL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364697]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Yao-Wen Chang
| |
| − |
| |
| − |
| |
| − | ===STRUCTURE AND METHOD FOR MRAM DEVICES ([[US Patent Application 18446563. STRUCTURE AND METHOD FOR MRAM DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446563]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Tsung-Chieh Hsiao
| |
| − |
| |
| − |
| |
| − | ===MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT ([[US Patent Application 18358685. MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358685]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Hai-Dang TRINH
| |
| − |
| |
| − |
| |
| − | ===METHODS OF FORMING MEMORY DEVICES ([[US Patent Application 18363751. METHODS OF FORMING MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363751]])===
| |
| − |
| |
| − |
| |
| − | '''Main Inventor'''
| |
| − |
| |
| − | Hung-Li Chiang
| |
