Difference between revisions of "Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on November 30th, 2023"
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==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023== | ==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023== | ||
| − | ===PARTICLE REMOVER AND METHOD ([[US Patent Application 18448963. PARTICLE REMOVER AND METHOD simplified abstract|18448963]])=== | + | ===PARTICLE REMOVER AND METHOD ([[US Patent Application 18448963. PARTICLE REMOVER AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448963]])=== |
| Line 32: | Line 9: | ||
| − | ===DEVICE FOR FORMING CONDUCTIVE POWDER ([[US Patent Application 18447161. DEVICE FOR FORMING CONDUCTIVE POWDER simplified abstract|18447161]])=== | + | ===DEVICE FOR FORMING CONDUCTIVE POWDER ([[US Patent Application 18447161. DEVICE FOR FORMING CONDUCTIVE POWDER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447161]])=== |
| Line 40: | Line 17: | ||
| − | ===POLISHING METROLOGY ([[US Patent Application 17898163. POLISHING METROLOGY simplified abstract|17898163]])=== | + | ===POLISHING METROLOGY ([[US Patent Application 17898163. POLISHING METROLOGY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17898163]])=== |
| Line 48: | Line 25: | ||
| − | ===MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE ([[US Patent Application 18364702. MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE simplified abstract|18364702]])=== | + | ===MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE ([[US Patent Application 18364702. MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364702]])=== |
| Line 56: | Line 33: | ||
| − | ===MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE ([[US Patent Application 18446741. MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE simplified abstract|18446741]])=== | + | ===MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE ([[US Patent Application 18446741. MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446741]])=== |
| Line 64: | Line 41: | ||
| − | ===WIRE-BOND DAMPER FOR SHOCK ABSORPTION ([[US Patent Application 18446740. WIRE-BOND DAMPER FOR SHOCK ABSORPTION simplified abstract|18446740]])=== | + | ===WIRE-BOND DAMPER FOR SHOCK ABSORPTION ([[US Patent Application 18446740. WIRE-BOND DAMPER FOR SHOCK ABSORPTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446740]])=== |
| Line 72: | Line 49: | ||
| − | ===DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE ([[US Patent Application 17825225. DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE simplified abstract|17825225]])=== | + | ===DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE ([[US Patent Application 17825225. DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825225]])=== |
| Line 80: | Line 57: | ||
| − | ===SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL ([[US Patent Application 18447543. SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL simplified abstract|18447543]])=== | + | ===SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL ([[US Patent Application 18447543. SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447543]])=== |
| Line 88: | Line 65: | ||
| − | ===TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS ([[US Patent Application 18150772. TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS simplified abstract|18150772]])=== | + | ===TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS ([[US Patent Application 18150772. TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18150772]])=== |
| Line 96: | Line 73: | ||
| − | ===TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS ([[US Patent Application 18170401. TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS simplified abstract|18170401]])=== | + | ===TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS ([[US Patent Application 18170401. TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18170401]])=== |
| Line 104: | Line 81: | ||
| − | ===METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18362983. METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE simplified abstract|18362983]])=== | + | ===METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18362983. METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362983]])=== |
| Line 112: | Line 89: | ||
| − | ===FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME ([[US Patent Application 18448032. FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME simplified abstract|18448032]])=== | + | ===FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME ([[US Patent Application 18448032. FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448032]])=== |
| Line 120: | Line 97: | ||
| − | ===METHOD OF MAKING PHOTONIC DEVICE ([[US Patent Application 18448046. METHOD OF MAKING PHOTONIC DEVICE simplified abstract|18448046]])=== | + | ===METHOD OF MAKING PHOTONIC DEVICE ([[US Patent Application 18448046. METHOD OF MAKING PHOTONIC DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448046]])=== |
| Line 128: | Line 105: | ||
| − | ===METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING ([[US Patent Application 18448095. METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING simplified abstract|18448095]])=== | + | ===METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING ([[US Patent Application 18448095. METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448095]])=== |
| Line 136: | Line 113: | ||
| − | ===METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING ([[US Patent Application 18358790. METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING simplified abstract|18358790]])=== | + | ===METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING ([[US Patent Application 18358790. METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358790]])=== |
| Line 144: | Line 121: | ||
| − | ===PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF ([[US Patent Application 18232674. PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF simplified abstract|18232674]])=== | + | ===PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF ([[US Patent Application 18232674. PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232674]])=== |
| Line 152: | Line 129: | ||
| − | ===PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME ([[US Patent Application 18362046. PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME simplified abstract|18362046]])=== | + | ===PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME ([[US Patent Application 18362046. PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362046]])=== |
| Line 160: | Line 137: | ||
| − | ===PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232264. PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract|18232264]])=== | + | ===PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232264. PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232264]])=== |
| Line 168: | Line 145: | ||
| − | ===PHOTORESIST MATERIALS AND ASSOCIATED METHODS ([[US Patent Application 18447568. PHOTORESIST MATERIALS AND ASSOCIATED METHODS simplified abstract|18447568]])=== | + | ===PHOTORESIST MATERIALS AND ASSOCIATED METHODS ([[US Patent Application 18447568. PHOTORESIST MATERIALS AND ASSOCIATED METHODS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447568]])=== |
| Line 176: | Line 153: | ||
| − | ===PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18232225. PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract|18232225]])=== | + | ===PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18232225. PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232225]])=== |
| Line 184: | Line 161: | ||
| − | ===PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232220. PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract|18232220]])=== | + | ===PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232220. PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232220]])=== |
| Line 192: | Line 169: | ||
| − | ===UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232774. UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract|18232774]])=== | + | ===UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232774. UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232774]])=== |
| Line 200: | Line 177: | ||
| − | ===PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18232717. PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract|18232717]])=== | + | ===PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18232717. PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232717]])=== |
| Line 208: | Line 185: | ||
| − | ===SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS ([[US Patent Application 18365529. SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS simplified abstract|18365529]])=== | + | ===SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS ([[US Patent Application 18365529. SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365529]])=== |
| Line 216: | Line 193: | ||
| − | ===METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR ([[US Patent Application 18358904. METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR simplified abstract|18358904]])=== | + | ===METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR ([[US Patent Application 18358904. METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358904]])=== |
| Line 224: | Line 201: | ||
| − | ===SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION ([[US Patent Application 18446870. SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION simplified abstract|18446870]])=== | + | ===SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION ([[US Patent Application 18446870. SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446870]])=== |
| Line 232: | Line 209: | ||
| − | ===OPTIMIZED MASK STITCHING ([[US Patent Application 18231070. OPTIMIZED MASK STITCHING simplified abstract|18231070]])=== | + | ===OPTIMIZED MASK STITCHING ([[US Patent Application 18231070. OPTIMIZED MASK STITCHING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231070]])=== |
| Line 240: | Line 217: | ||
| − | ===ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18232745. ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract|18232745]])=== | + | ===ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18232745. ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232745]])=== |
| Line 248: | Line 225: | ||
| − | ===MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW ([[US Patent Application 18447361. MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW simplified abstract|18447361]])=== | + | ===MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW ([[US Patent Application 18447361. MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447361]])=== |
| Line 256: | Line 233: | ||
| − | ===SEMICONDUCTOR WAFER COOLING ([[US Patent Application 18362037. SEMICONDUCTOR WAFER COOLING simplified abstract|18362037]])=== | + | ===SEMICONDUCTOR WAFER COOLING ([[US Patent Application 18362037. SEMICONDUCTOR WAFER COOLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362037]])=== |
| Line 264: | Line 241: | ||
| − | ===MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME ([[US Patent Application 18355222. MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME simplified abstract|18355222]])=== | + | ===MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME ([[US Patent Application 18355222. MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18355222]])=== |
| Line 272: | Line 249: | ||
| − | ===FAULT DIAGNOSTICS ([[US Patent Application 18303219. FAULT DIAGNOSTICS simplified abstract|18303219]])=== | + | ===FAULT DIAGNOSTICS ([[US Patent Application 18303219. FAULT DIAGNOSTICS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18303219]])=== |
| Line 280: | Line 257: | ||
| − | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 17821559. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract|17821559]])=== | + | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 17821559. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17821559]])=== |
| Line 288: | Line 265: | ||
| − | ===METHOD FOR CHIP INTEGRATION ([[US Patent Application 17828648. METHOD FOR CHIP INTEGRATION simplified abstract|17828648]])=== | + | ===METHOD FOR CHIP INTEGRATION ([[US Patent Application 17828648. METHOD FOR CHIP INTEGRATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828648]])=== |
| Line 296: | Line 273: | ||
| − | ===SEMICONDUCTOR DEVICE ([[US Patent Application 18361815. SEMICONDUCTOR DEVICE simplified abstract|18361815]])=== | + | ===SEMICONDUCTOR DEVICE ([[US Patent Application 18361815. SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361815]])=== |
| Line 304: | Line 281: | ||
| − | ===ANTI-FUSE ARRAY ([[US Patent Application 18446684. ANTI-FUSE ARRAY simplified abstract|18446684]])=== | + | ===ANTI-FUSE ARRAY ([[US Patent Application 18446684. ANTI-FUSE ARRAY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446684]])=== |
| Line 312: | Line 289: | ||
| − | ===INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 18446771. INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME simplified abstract|18446771]])=== | + | ===INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 18446771. INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446771]])=== |
| Line 320: | Line 297: | ||
| − | ===METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS ([[US Patent Application 18447964. METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS simplified abstract|18447964]])=== | + | ===METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS ([[US Patent Application 18447964. METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447964]])=== |
| Line 328: | Line 305: | ||
| − | ===SILICON PHOTONICS SYSTEM ([[US Patent Application 18155980. SILICON PHOTONICS SYSTEM simplified abstract|18155980]])=== | + | ===SILICON PHOTONICS SYSTEM ([[US Patent Application 18155980. SILICON PHOTONICS SYSTEM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18155980]])=== |
| Line 336: | Line 313: | ||
| − | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 18354377. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract|18354377]])=== | + | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 18354377. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18354377]])=== |
| Line 344: | Line 321: | ||
| − | ===TRANSMISSION GATE STRUCTURE ([[US Patent Application 18362195. TRANSMISSION GATE STRUCTURE simplified abstract|18362195]])=== | + | ===TRANSMISSION GATE STRUCTURE ([[US Patent Application 18362195. TRANSMISSION GATE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362195]])=== |
| Line 352: | Line 329: | ||
| − | ===SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT ([[US Patent Application 18448143. SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT simplified abstract|18448143]])=== | + | ===SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT ([[US Patent Application 18448143. SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448143]])=== |
| Line 360: | Line 337: | ||
| − | ===NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY ([[US Patent Application 17824306. NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY simplified abstract|17824306]])=== | + | ===NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY ([[US Patent Application 17824306. NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824306]])=== |
| Line 368: | Line 345: | ||
| − | ===MEMORY DEVICE WITH SOURCE LINE CONTROL ([[US Patent Application 18232542. MEMORY DEVICE WITH SOURCE LINE CONTROL simplified abstract|18232542]])=== | + | ===MEMORY DEVICE WITH SOURCE LINE CONTROL ([[US Patent Application 18232542. MEMORY DEVICE WITH SOURCE LINE CONTROL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232542]])=== |
| Line 376: | Line 353: | ||
| − | ===Systems and Methods for Controlling Power Management Operations in a Memory Device ([[US Patent Application 18446818. Systems and Methods for Controlling Power Management Operations in a Memory Device simplified abstract|18446818]])=== | + | ===Systems and Methods for Controlling Power Management Operations in a Memory Device ([[US Patent Application 18446818. Systems and Methods for Controlling Power Management Operations in a Memory Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446818]])=== |
| Line 384: | Line 361: | ||
| − | ===ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES ([[US Patent Application 18446072. ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES simplified abstract|18446072]])=== | + | ===ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES ([[US Patent Application 18446072. ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446072]])=== |
| Line 392: | Line 369: | ||
| − | ===FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR ([[US Patent Application 17826180. FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR simplified abstract|17826180]])=== | + | ===FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR ([[US Patent Application 17826180. FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826180]])=== |
| Line 400: | Line 377: | ||
| − | ===MEMORY DEVICE WITH REDUCED AREA ([[US Patent Application 17752662. MEMORY DEVICE WITH REDUCED AREA simplified abstract|17752662]])=== | + | ===MEMORY DEVICE WITH REDUCED AREA ([[US Patent Application 17752662. MEMORY DEVICE WITH REDUCED AREA simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752662]])=== |
| Line 408: | Line 385: | ||
| − | ===THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY ([[US Patent Application 18232539. THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY simplified abstract|18232539]])=== | + | ===THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY ([[US Patent Application 18232539. THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232539]])=== |
| Line 416: | Line 393: | ||
| − | ===NON-VOLATILE MEMORY CIRCUIT AND METHOD ([[US Patent Application 18448152. NON-VOLATILE MEMORY CIRCUIT AND METHOD simplified abstract|18448152]])=== | + | ===NON-VOLATILE MEMORY CIRCUIT AND METHOD ([[US Patent Application 18448152. NON-VOLATILE MEMORY CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448152]])=== |
| Line 424: | Line 401: | ||
| − | ===FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL ([[US Patent Application 18447410. FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL simplified abstract|18447410]])=== | + | ===FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL ([[US Patent Application 18447410. FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447410]])=== |
| Line 432: | Line 409: | ||
| − | ===DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING ([[US Patent Application 18231165. DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING simplified abstract|18231165]])=== | + | ===DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING ([[US Patent Application 18231165. DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231165]])=== |
| Line 440: | Line 417: | ||
| − | ===SEMICONDUCTOR TOOL FOR COPPER DEPOSITION ([[US Patent Application 18447557. SEMICONDUCTOR TOOL FOR COPPER DEPOSITION simplified abstract|18447557]])=== | + | ===SEMICONDUCTOR TOOL FOR COPPER DEPOSITION ([[US Patent Application 18447557. SEMICONDUCTOR TOOL FOR COPPER DEPOSITION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447557]])=== |
| Line 448: | Line 425: | ||
| − | ===METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS ([[US Patent Application 18225576. METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS simplified abstract|18225576]])=== | + | ===METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS ([[US Patent Application 18225576. METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18225576]])=== |
| Line 456: | Line 433: | ||
| − | ===SEMICONDUCTOR DEVICE PRE-CLEANING ([[US Patent Application 17804447. SEMICONDUCTOR DEVICE PRE-CLEANING simplified abstract|17804447]])=== | + | ===SEMICONDUCTOR DEVICE PRE-CLEANING ([[US Patent Application 17804447. SEMICONDUCTOR DEVICE PRE-CLEANING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804447]])=== |
| Line 464: | Line 441: | ||
| − | ===APPARATUS FOR ELECTRO-CHEMICAL PLATING ([[US Patent Application 18231196. APPARATUS FOR ELECTRO-CHEMICAL PLATING simplified abstract|18231196]])=== | + | ===APPARATUS FOR ELECTRO-CHEMICAL PLATING ([[US Patent Application 18231196. APPARATUS FOR ELECTRO-CHEMICAL PLATING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231196]])=== |
| Line 472: | Line 449: | ||
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 17829154. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract|17829154]])=== | + | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 17829154. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17829154]])=== |
| Line 480: | Line 457: | ||
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18232758. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract|18232758]])=== | + | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18232758. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232758]])=== |
| Line 488: | Line 465: | ||
| − | ===METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL ([[US Patent Application 18447810. METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL simplified abstract|18447810]])=== | + | ===METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL ([[US Patent Application 18447810. METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447810]])=== |
| Line 496: | Line 473: | ||
| − | ===NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL ([[US Patent Application 18446652. NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL simplified abstract|18446652]])=== | + | ===NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL ([[US Patent Application 18446652. NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446652]])=== |
| Line 504: | Line 481: | ||
| − | ===CHEMICAL DISPENSING SYSTEM ([[US Patent Application 18447353. CHEMICAL DISPENSING SYSTEM simplified abstract|18447353]])=== | + | ===CHEMICAL DISPENSING SYSTEM ([[US Patent Application 18447353. CHEMICAL DISPENSING SYSTEM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447353]])=== |
| Line 512: | Line 489: | ||
| − | ===SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE ([[US Patent Application 18358517. SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE simplified abstract|18358517]])=== | + | ===SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE ([[US Patent Application 18358517. SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358517]])=== |
| Line 520: | Line 497: | ||
| − | ===SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF ([[US Patent Application 18446549. SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF simplified abstract|18446549]])=== | + | ===SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF ([[US Patent Application 18446549. SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446549]])=== |
| Line 528: | Line 505: | ||
| − | ===ETCH METHOD FOR INTERCONNECT STRUCTURE ([[US Patent Application 18447134. ETCH METHOD FOR INTERCONNECT STRUCTURE simplified abstract|18447134]])=== | + | ===ETCH METHOD FOR INTERCONNECT STRUCTURE ([[US Patent Application 18447134. ETCH METHOD FOR INTERCONNECT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447134]])=== |
| Line 536: | Line 513: | ||
| − | ===LOCAL INTERCONNECT ([[US Patent Application 18447549. LOCAL INTERCONNECT simplified abstract|18447549]])=== | + | ===LOCAL INTERCONNECT ([[US Patent Application 18447549. LOCAL INTERCONNECT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447549]])=== |
| Line 544: | Line 521: | ||
| − | ===SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME ([[US Patent Application 18230338. SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME simplified abstract|18230338]])=== | + | ===SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME ([[US Patent Application 18230338. SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18230338]])=== |
| Line 552: | Line 529: | ||
| − | ===METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES ([[US Patent Application 17825307. METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES simplified abstract|17825307]])=== | + | ===METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES ([[US Patent Application 17825307. METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825307]])=== |
| Line 560: | Line 537: | ||
| − | ===METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH ([[US Patent Application 17825678. METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH simplified abstract|17825678]])=== | + | ===METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH ([[US Patent Application 17825678. METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825678]])=== |
| Line 568: | Line 545: | ||
| − | ===GATE CONTACT STRUCTURE ([[US Patent Application 18446326. GATE CONTACT STRUCTURE simplified abstract|18446326]])=== | + | ===GATE CONTACT STRUCTURE ([[US Patent Application 18446326. GATE CONTACT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446326]])=== |
| Line 576: | Line 553: | ||
| − | ===METAL GATE PROCESS AND RELATED STRUCTURE ([[US Patent Application 17804146. METAL GATE PROCESS AND RELATED STRUCTURE simplified abstract|17804146]])=== | + | ===METAL GATE PROCESS AND RELATED STRUCTURE ([[US Patent Application 17804146. METAL GATE PROCESS AND RELATED STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804146]])=== |
| Line 584: | Line 561: | ||
| − | ===METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION ([[US Patent Application 18360814. METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION simplified abstract|18360814]])=== | + | ===METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION ([[US Patent Application 18360814. METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360814]])=== |
| Line 592: | Line 569: | ||
| − | ===METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE ([[US Patent Application 18361501. METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE simplified abstract|18361501]])=== | + | ===METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE ([[US Patent Application 18361501. METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361501]])=== |
| Line 600: | Line 577: | ||
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18447125. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18447125]])=== | + | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18447125. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447125]])=== |
| Line 608: | Line 585: | ||
| − | ===SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824249. SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract|17824249]])=== | + | ===SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824249. SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824249]])=== |
| Line 616: | Line 593: | ||
| − | ===REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES ([[US Patent Application 18359747. REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES simplified abstract|18359747]])=== | + | ===REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES ([[US Patent Application 18359747. REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359747]])=== |
| Line 624: | Line 601: | ||
| − | ===HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER ([[US Patent Application 18447239. HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER simplified abstract|18447239]])=== | + | ===HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER ([[US Patent Application 18447239. HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447239]])=== |
| Line 632: | Line 609: | ||
| − | ===METHOD FOR FORMING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824263. METHOD FOR FORMING SEMICONDUCTOR STRUCTURE simplified abstract|17824263]])=== | + | ===METHOD FOR FORMING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824263. METHOD FOR FORMING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824263]])=== |
| Line 640: | Line 617: | ||
| − | ===MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION ([[US Patent Application 18359206. MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION simplified abstract|18359206]])=== | + | ===MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION ([[US Patent Application 18359206. MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359206]])=== |
| Line 648: | Line 625: | ||
| − | ===SYSTEMS AND METHODS OF TESTING MEMORY DEVICES ([[US Patent Application 18232518. SYSTEMS AND METHODS OF TESTING MEMORY DEVICES simplified abstract|18232518]])=== | + | ===SYSTEMS AND METHODS OF TESTING MEMORY DEVICES ([[US Patent Application 18232518. SYSTEMS AND METHODS OF TESTING MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232518]])=== |
| Line 656: | Line 633: | ||
| − | ===SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE ([[US Patent Application 18232520. SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE simplified abstract|18232520]])=== | + | ===SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE ([[US Patent Application 18232520. SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232520]])=== |
| Line 664: | Line 641: | ||
| − | ===MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE ([[US Patent Application 18363742. MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE simplified abstract|18363742]])=== | + | ===MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE ([[US Patent Application 18363742. MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363742]])=== |
| Line 672: | Line 649: | ||
| − | ===STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE ([[US Patent Application 18446076. STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE simplified abstract|18446076]])=== | + | ===STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE ([[US Patent Application 18446076. STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446076]])=== |
| Line 680: | Line 657: | ||
| − | ===SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING ([[US Patent Application 18447927. SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING simplified abstract|18447927]])=== | + | ===SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING ([[US Patent Application 18447927. SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447927]])=== |
| Line 688: | Line 665: | ||
| − | ===SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17827992. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract|17827992]])=== | + | ===SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17827992. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827992]])=== |
| Line 696: | Line 673: | ||
| − | ===INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME ([[US Patent Application 17829243. INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME simplified abstract|17829243]])=== | + | ===INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME ([[US Patent Application 17829243. INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17829243]])=== |
| Line 704: | Line 681: | ||
| − | ===VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS ([[US Patent Application 17825336. VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS simplified abstract|17825336]])=== | + | ===VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS ([[US Patent Application 17825336. VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825336]])=== |
| Line 712: | Line 689: | ||
| − | ===SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18361917. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract|18361917]])=== | + | ===SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18361917. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361917]])=== |
| Line 720: | Line 697: | ||
| − | ===Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via ([[US Patent Application 18447871. Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via simplified abstract|18447871]])=== | + | ===Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via ([[US Patent Application 18447871. Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447871]])=== |
| Line 728: | Line 705: | ||
| − | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18359864. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract|18359864]])=== | + | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18359864. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359864]])=== |
| Line 736: | Line 713: | ||
| − | ===SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH ([[US Patent Application 18232523. SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH simplified abstract|18232523]])=== | + | ===SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH ([[US Patent Application 18232523. SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232523]])=== |
| Line 744: | Line 721: | ||
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18363766. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|18363766]])=== | + | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18363766. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363766]])=== |
| Line 752: | Line 729: | ||
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446873. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18446873]])=== | + | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446873. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446873]])=== |
| Line 760: | Line 737: | ||
| − | ===BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE ([[US Patent Application 18447722. BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE simplified abstract|18447722]])=== | + | ===BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE ([[US Patent Application 18447722. BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447722]])=== |
| Line 768: | Line 745: | ||
| − | ===SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING ([[US Patent Application 17825698. SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING simplified abstract|17825698]])=== | + | ===SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING ([[US Patent Application 17825698. SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825698]])=== |
| Line 776: | Line 753: | ||
| − | ===SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD ([[US Patent Application 17752704. SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD simplified abstract|17752704]])=== | + | ===SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD ([[US Patent Application 17752704. SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752704]])=== |
| Line 784: | Line 761: | ||
| − | ===DIAGONAL VIA STRUCTURE ([[US Patent Application 18448125. DIAGONAL VIA STRUCTURE simplified abstract|18448125]])=== | + | ===DIAGONAL VIA STRUCTURE ([[US Patent Application 18448125. DIAGONAL VIA STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448125]])=== |
| Line 792: | Line 769: | ||
| − | ===SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT ([[US Patent Application 18232306. SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT simplified abstract|18232306]])=== | + | ===SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT ([[US Patent Application 18232306. SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232306]])=== |
| Line 800: | Line 777: | ||
| − | ===ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY ([[US Patent Application 18446025. ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY simplified abstract|18446025]])=== | + | ===ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY ([[US Patent Application 18446025. ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446025]])=== |
| Line 808: | Line 785: | ||
| − | ===FIRST METAL STRUCTURE, LAYOUT, AND METHOD ([[US Patent Application 17752737. FIRST METAL STRUCTURE, LAYOUT, AND METHOD simplified abstract|17752737]])=== | + | ===FIRST METAL STRUCTURE, LAYOUT, AND METHOD ([[US Patent Application 17752737. FIRST METAL STRUCTURE, LAYOUT, AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752737]])=== |
| Line 816: | Line 793: | ||
| − | ===POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS ([[US Patent Application 18361666. POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS simplified abstract|18361666]])=== | + | ===POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS ([[US Patent Application 18361666. POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361666]])=== |
| Line 824: | Line 801: | ||
| − | ===METHOD OF MANUFACTURING INTEGRATED CIRCUIT ([[US Patent Application 18447572. METHOD OF MANUFACTURING INTEGRATED CIRCUIT simplified abstract|18447572]])=== | + | ===METHOD OF MANUFACTURING INTEGRATED CIRCUIT ([[US Patent Application 18447572. METHOD OF MANUFACTURING INTEGRATED CIRCUIT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447572]])=== |
| Line 832: | Line 809: | ||
| − | ===CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES ([[US Patent Application 18448005. CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES simplified abstract|18448005]])=== | + | ===CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES ([[US Patent Application 18448005. CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448005]])=== |
| Line 840: | Line 817: | ||
| − | ===METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS ([[US Patent Application 18448028. METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS simplified abstract|18448028]])=== | + | ===METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS ([[US Patent Application 18448028. METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448028]])=== |
| Line 848: | Line 825: | ||
| − | ===INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT ([[US Patent Application 18360012. INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT simplified abstract|18360012]])=== | + | ===INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT ([[US Patent Application 18360012. INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360012]])=== |
| Line 856: | Line 833: | ||
| − | ===INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS ([[US Patent Application 17825345. INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS simplified abstract|17825345]])=== | + | ===INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS ([[US Patent Application 17825345. INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825345]])=== |
| Line 864: | Line 841: | ||
| − | ===SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE ([[US Patent Application 17825741. SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE simplified abstract|17825741]])=== | + | ===SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE ([[US Patent Application 17825741. SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825741]])=== |
| Line 872: | Line 849: | ||
| − | ===SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF ([[US Patent Application 17823063. SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF simplified abstract|17823063]])=== | + | ===SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF ([[US Patent Application 17823063. SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17823063]])=== |
| Line 880: | Line 857: | ||
| − | ===SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION ([[US Patent Application 17824353. SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION simplified abstract|17824353]])=== | + | ===SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION ([[US Patent Application 17824353. SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824353]])=== |
| Line 888: | Line 865: | ||
| − | ===SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME ([[US Patent Application 18230999. SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME simplified abstract|18230999]])=== | + | ===SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME ([[US Patent Application 18230999. SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18230999]])=== |
| Line 896: | Line 873: | ||
| − | ===SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS ([[US Patent Application 17824330. SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS simplified abstract|17824330]])=== | + | ===SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS ([[US Patent Application 17824330. SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824330]])=== |
| Line 904: | Line 881: | ||
| − | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18361953. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract|18361953]])=== | + | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18361953. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361953]])=== |
| Line 912: | Line 889: | ||
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME ([[US Patent Application 18447979. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME simplified abstract|18447979]])=== | + | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME ([[US Patent Application 18447979. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447979]])=== |
| Line 920: | Line 897: | ||
| − | ===SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME ([[US Patent Application 17826604. SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME simplified abstract|17826604]])=== | + | ===SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME ([[US Patent Application 17826604. SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826604]])=== |
| Line 928: | Line 905: | ||
| − | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME ([[US Patent Application 18229682. SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract|18229682]])=== | + | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME ([[US Patent Application 18229682. SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18229682]])=== |
| Line 936: | Line 913: | ||
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18362862. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|18362862]])=== | + | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18362862. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362862]])=== |
| Line 944: | Line 921: | ||
| − | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 17828981. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract|17828981]])=== | + | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 17828981. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828981]])=== |
| Line 952: | Line 929: | ||
| − | ===LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE ([[US Patent Application 18366831. LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE simplified abstract|18366831]])=== | + | ===LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE ([[US Patent Application 18366831. LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366831]])=== |
| Line 960: | Line 937: | ||
| − | ===METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE ([[US Patent Application 18360214. METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE simplified abstract|18360214]])=== | + | ===METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE ([[US Patent Application 18360214. METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360214]])=== |
| Line 968: | Line 945: | ||
| − | ===IMAGE SENSOR WITH A HIGH ABSORPTION LAYER ([[US Patent Application 18364662. IMAGE SENSOR WITH A HIGH ABSORPTION LAYER simplified abstract|18364662]])=== | + | ===IMAGE SENSOR WITH A HIGH ABSORPTION LAYER ([[US Patent Application 18364662. IMAGE SENSOR WITH A HIGH ABSORPTION LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364662]])=== |
| Line 976: | Line 953: | ||
| − | ===PIXEL SENSOR INCLUDING A TRANSFER FINFET ([[US Patent Application 18447340. PIXEL SENSOR INCLUDING A TRANSFER FINFET simplified abstract|18447340]])=== | + | ===PIXEL SENSOR INCLUDING A TRANSFER FINFET ([[US Patent Application 18447340. PIXEL SENSOR INCLUDING A TRANSFER FINFET simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447340]])=== |
| Line 984: | Line 961: | ||
| − | ===EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR ([[US Patent Application 18364667. EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR simplified abstract|18364667]])=== | + | ===EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR ([[US Patent Application 18364667. EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364667]])=== |
| Line 992: | Line 969: | ||
| − | ===IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION ([[US Patent Application 18446572. IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION simplified abstract|18446572]])=== | + | ===IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION ([[US Patent Application 18446572. IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446572]])=== |
| Line 1,000: | Line 977: | ||
| − | ===METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY ([[US Patent Application 18360966. METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY simplified abstract|18360966]])=== | + | ===METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY ([[US Patent Application 18360966. METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360966]])=== |
| Line 1,008: | Line 985: | ||
| − | ===OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE ([[US Patent Application 17824183. OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE simplified abstract|17824183]])=== | + | ===OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE ([[US Patent Application 17824183. OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824183]])=== |
| Line 1,016: | Line 993: | ||
| − | ===BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR ([[US Patent Application 18364682. BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR simplified abstract|18364682]])=== | + | ===BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR ([[US Patent Application 18364682. BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364682]])=== |
| Line 1,024: | Line 1,001: | ||
| − | ===DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR ([[US Patent Application 18364734. DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR simplified abstract|18364734]])=== | + | ===DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR ([[US Patent Application 18364734. DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364734]])=== |
| Line 1,032: | Line 1,009: | ||
| − | ===INDUCTIVE DEVICE ([[US Patent Application 18447482. INDUCTIVE DEVICE simplified abstract|18447482]])=== | + | ===INDUCTIVE DEVICE ([[US Patent Application 18447482. INDUCTIVE DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447482]])=== |
| Line 1,040: | Line 1,017: | ||
| − | ===Resistor Structure ([[US Patent Application 18358557. Resistor Structure simplified abstract|18358557]])=== | + | ===Resistor Structure ([[US Patent Application 18358557. Resistor Structure simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358557]])=== |
| Line 1,048: | Line 1,025: | ||
| − | ===A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE ([[US Patent Application 18366156. A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE simplified abstract|18366156]])=== | + | ===A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE ([[US Patent Application 18366156. A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366156]])=== |
| Line 1,056: | Line 1,033: | ||
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17824436. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|17824436]])=== | + | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17824436. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824436]])=== |
| Line 1,064: | Line 1,041: | ||
| − | ===SUPER JUNCTION STRUCTURE ([[US Patent Application 18448013. SUPER JUNCTION STRUCTURE simplified abstract|18448013]])=== | + | ===SUPER JUNCTION STRUCTURE ([[US Patent Application 18448013. SUPER JUNCTION STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448013]])=== |
| Line 1,072: | Line 1,049: | ||
| − | ===NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION ([[US Patent Application 18232545. NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION simplified abstract|18232545]])=== | + | ===NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION ([[US Patent Application 18232545. NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232545]])=== |
| Line 1,080: | Line 1,057: | ||
| − | ===SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME ([[US Patent Application 18366210. SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME simplified abstract|18366210]])=== | + | ===SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME ([[US Patent Application 18366210. SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366210]])=== |
| Line 1,088: | Line 1,065: | ||
| − | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17824329. SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME simplified abstract|17824329]])=== | + | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17824329. SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824329]])=== |
| Line 1,096: | Line 1,073: | ||
| − | ===GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME ([[US Patent Application 17804751. GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME simplified abstract|17804751]])=== | + | ===GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME ([[US Patent Application 17804751. GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804751]])=== |
| Line 1,104: | Line 1,081: | ||
| − | ===EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION ([[US Patent Application 17824915. EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION simplified abstract|17824915]])=== | + | ===EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION ([[US Patent Application 17824915. EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824915]])=== |
| Line 1,112: | Line 1,089: | ||
| − | ===INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE ([[US Patent Application 18363077. INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE simplified abstract|18363077]])=== | + | ===INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE ([[US Patent Application 18363077. INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363077]])=== |
| Line 1,120: | Line 1,097: | ||
| − | ===SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF ([[US Patent Application 17752211. SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF simplified abstract|17752211]])=== | + | ===SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF ([[US Patent Application 17752211. SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752211]])=== |
| Line 1,128: | Line 1,105: | ||
| − | ===Semiconductor Gate-All-Around Device ([[US Patent Application 18360080. Semiconductor Gate-All-Around Device simplified abstract|18360080]])=== | + | ===Semiconductor Gate-All-Around Device ([[US Patent Application 18360080. Semiconductor Gate-All-Around Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360080]])=== |
| Line 1,136: | Line 1,113: | ||
| − | ===PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS ([[US Patent Application 18361262. PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS simplified abstract|18361262]])=== | + | ===PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS ([[US Patent Application 18361262. PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361262]])=== |
| Line 1,144: | Line 1,121: | ||
| − | ===SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER ([[US Patent Application 18446864. SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER simplified abstract|18446864]])=== | + | ===SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER ([[US Patent Application 18446864. SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446864]])=== |
| Line 1,152: | Line 1,129: | ||
| − | ===SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF ([[US Patent Application 18360085. SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF simplified abstract|18360085]])=== | + | ===SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF ([[US Patent Application 18360085. SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360085]])=== |
| Line 1,160: | Line 1,137: | ||
| − | ===SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION ([[US Patent Application 18447344. SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION simplified abstract|18447344]])=== | + | ===SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION ([[US Patent Application 18447344. SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447344]])=== |
| Line 1,168: | Line 1,145: | ||
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES ([[US Patent Application 17752461. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES simplified abstract|17752461]])=== | + | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES ([[US Patent Application 17752461. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752461]])=== |
| Line 1,176: | Line 1,153: | ||
| − | ===SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME ([[US Patent Application 17825411. SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME simplified abstract|17825411]])=== | + | ===SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME ([[US Patent Application 17825411. SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825411]])=== |
| Line 1,184: | Line 1,161: | ||
| − | ===SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF ([[US Patent Application 18447183. SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF simplified abstract|18447183]])=== | + | ===SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF ([[US Patent Application 18447183. SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447183]])=== |
| Line 1,192: | Line 1,169: | ||
| − | ===SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF ([[US Patent Application 17804125. SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF simplified abstract|17804125]])=== | + | ===SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF ([[US Patent Application 17804125. SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804125]])=== |
| Line 1,200: | Line 1,177: | ||
| − | ===Spacer Structures for Nano-Sheet-Based Devices ([[US Patent Application 18446733. Spacer Structures for Nano-Sheet-Based Devices simplified abstract|18446733]])=== | + | ===Spacer Structures for Nano-Sheet-Based Devices ([[US Patent Application 18446733. Spacer Structures for Nano-Sheet-Based Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446733]])=== |
| Line 1,208: | Line 1,185: | ||
| − | ===3D CAPACITOR AND METHOD OF MANUFACTURING SAME ([[US Patent Application 18366596. 3D CAPACITOR AND METHOD OF MANUFACTURING SAME simplified abstract|18366596]])=== | + | ===3D CAPACITOR AND METHOD OF MANUFACTURING SAME ([[US Patent Application 18366596. 3D CAPACITOR AND METHOD OF MANUFACTURING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366596]])=== |
| Line 1,216: | Line 1,193: | ||
| − | ===GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE ([[US Patent Application 17824690. GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE simplified abstract|17824690]])=== | + | ===GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE ([[US Patent Application 17824690. GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824690]])=== |
| Line 1,224: | Line 1,201: | ||
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17826174. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|17826174]])=== | + | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17826174. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826174]])=== |
| Line 1,232: | Line 1,209: | ||
| − | ===METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE ([[US Patent Application 18232289. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE simplified abstract|18232289]])=== | + | ===METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE ([[US Patent Application 18232289. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232289]])=== |
| Line 1,240: | Line 1,217: | ||
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18232544. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18232544]])=== | + | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18232544. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232544]])=== |
| Line 1,248: | Line 1,225: | ||
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE ([[US Patent Application 18447489. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE simplified abstract|18447489]])=== | + | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE ([[US Patent Application 18447489. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447489]])=== |
| Line 1,256: | Line 1,233: | ||
| − | ===INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE ([[US Patent Application 18364679. INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE simplified abstract|18364679]])=== | + | ===INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE ([[US Patent Application 18364679. INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364679]])=== |
| Line 1,264: | Line 1,241: | ||
| − | ===FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME ([[US Patent Application 17827755. FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME simplified abstract|17827755]])=== | + | ===FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME ([[US Patent Application 17827755. FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827755]])=== |
| Line 1,272: | Line 1,249: | ||
| − | ===METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE ([[US Patent Application 18446539. METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE simplified abstract|18446539]])=== | + | ===METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE ([[US Patent Application 18446539. METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446539]])=== |
| Line 1,280: | Line 1,257: | ||
| − | ===HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION ([[US Patent Application 17804438. HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION simplified abstract|17804438]])=== | + | ===HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION ([[US Patent Application 17804438. HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804438]])=== |
| Line 1,288: | Line 1,265: | ||
| − | ===ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS ([[US Patent Application 18446664. ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS simplified abstract|18446664]])=== | + | ===ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS ([[US Patent Application 18446664. ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446664]])=== |
| Line 1,296: | Line 1,273: | ||
| − | ===SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE ([[US Patent Application 17824669. SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE simplified abstract|17824669]])=== | + | ===SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE ([[US Patent Application 17824669. SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824669]])=== |
| Line 1,304: | Line 1,281: | ||
| − | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17825516. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract|17825516]])=== | + | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17825516. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825516]])=== |
| Line 1,312: | Line 1,289: | ||
| − | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 18359690. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract|18359690]])=== | + | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 18359690. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359690]])=== |
| Line 1,320: | Line 1,297: | ||
| − | ===METHOD OF MAKING DECOUPLING CAPACITOR ([[US Patent Application 18447194. METHOD OF MAKING DECOUPLING CAPACITOR simplified abstract|18447194]])=== | + | ===METHOD OF MAKING DECOUPLING CAPACITOR ([[US Patent Application 18447194. METHOD OF MAKING DECOUPLING CAPACITOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447194]])=== |
| Line 1,328: | Line 1,305: | ||
| − | ===SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS ([[US Patent Application 17827251. SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS simplified abstract|17827251]])=== | + | ===SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS ([[US Patent Application 17827251. SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827251]])=== |
| Line 1,336: | Line 1,313: | ||
| − | ===DECOUPLING FINFET CAPACITORS ([[US Patent Application 18358464. DECOUPLING FINFET CAPACITORS simplified abstract|18358464]])=== | + | ===DECOUPLING FINFET CAPACITORS ([[US Patent Application 18358464. DECOUPLING FINFET CAPACITORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358464]])=== |
| Line 1,344: | Line 1,321: | ||
| − | ===VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING ([[US Patent Application 18446031. VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING simplified abstract|18446031]])=== | + | ===VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING ([[US Patent Application 18446031. VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446031]])=== |
| Line 1,352: | Line 1,329: | ||
| − | ===CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME ([[US Patent Application 18362916. CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME simplified abstract|18362916]])=== | + | ===CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME ([[US Patent Application 18362916. CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362916]])=== |
| Line 1,360: | Line 1,337: | ||
| − | ===DATA RETENTION CIRCUIT AND METHOD ([[US Patent Application 18363192. DATA RETENTION CIRCUIT AND METHOD simplified abstract|18363192]])=== | + | ===DATA RETENTION CIRCUIT AND METHOD ([[US Patent Application 18363192. DATA RETENTION CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363192]])=== |
| Line 1,368: | Line 1,345: | ||
| − | ===Flip Flop Circuit ([[US Patent Application 18366981. Flip Flop Circuit simplified abstract|18366981]])=== | + | ===Flip Flop Circuit ([[US Patent Application 18366981. Flip Flop Circuit simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366981]])=== |
| Line 1,376: | Line 1,353: | ||
| − | ===SYSTEM AND SEMICONDUCTOR DEVICE THEREIN ([[US Patent Application 17828834. SYSTEM AND SEMICONDUCTOR DEVICE THEREIN simplified abstract|17828834]])=== | + | ===SYSTEM AND SEMICONDUCTOR DEVICE THEREIN ([[US Patent Application 17828834. SYSTEM AND SEMICONDUCTOR DEVICE THEREIN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828834]])=== |
| Line 1,384: | Line 1,361: | ||
| − | ===POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION ([[US Patent Application 17828581. POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION simplified abstract|17828581]])=== | + | ===POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION ([[US Patent Application 17828581. POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828581]])=== |
| Line 1,392: | Line 1,369: | ||
| − | ===Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals ([[US Patent Application 18446849. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract|18446849]])=== | + | ===Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals ([[US Patent Application 18446849. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446849]])=== |
| Line 1,400: | Line 1,377: | ||
| − | ===Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals ([[US Patent Application 18447372. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract|18447372]])=== | + | ===Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals ([[US Patent Application 18447372. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447372]])=== |
| Line 1,408: | Line 1,385: | ||
| − | ===Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation ([[US Patent Application 18446881. Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation simplified abstract|18446881]])=== | + | ===Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation ([[US Patent Application 18446881. Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446881]])=== |
| Line 1,416: | Line 1,393: | ||
| − | ===Programmable Regulator Voltage Controlled Ring Oscillator ([[US Patent Application 18366742. Programmable Regulator Voltage Controlled Ring Oscillator simplified abstract|18366742]])=== | + | ===Programmable Regulator Voltage Controlled Ring Oscillator ([[US Patent Application 18366742. Programmable Regulator Voltage Controlled Ring Oscillator simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366742]])=== |
| Line 1,424: | Line 1,401: | ||
| − | ===Circuits and Methods for a Noise Shaping Analog To Digital Converter ([[US Patent Application 18361949. Circuits and Methods for a Noise Shaping Analog To Digital Converter simplified abstract|18361949]])=== | + | ===Circuits and Methods for a Noise Shaping Analog To Digital Converter ([[US Patent Application 18361949. Circuits and Methods for a Noise Shaping Analog To Digital Converter simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361949]])=== |
| Line 1,432: | Line 1,409: | ||
| − | ===METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE ([[US Patent Application 18361816. METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE simplified abstract|18361816]])=== | + | ===METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE ([[US Patent Application 18361816. METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361816]])=== |
| Line 1,440: | Line 1,417: | ||
| − | ===EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY ([[US Patent Application 18231017. EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY simplified abstract|18231017]])=== | + | ===EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY ([[US Patent Application 18231017. EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231017]])=== |
| Line 1,448: | Line 1,425: | ||
| − | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17826225. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract|17826225]])=== | + | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17826225. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826225]])=== |
| Line 1,456: | Line 1,433: | ||
| − | ===IC INCLUDING STANDARD CELLS AND SRAM CELLS ([[US Patent Application 18361185. IC INCLUDING STANDARD CELLS AND SRAM CELLS simplified abstract|18361185]])=== | + | ===IC INCLUDING STANDARD CELLS AND SRAM CELLS ([[US Patent Application 18361185. IC INCLUDING STANDARD CELLS AND SRAM CELLS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361185]])=== |
| Line 1,464: | Line 1,441: | ||
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446094. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18446094]])=== | + | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446094. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446094]])=== |
| Line 1,472: | Line 1,449: | ||
| − | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17828123. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|17828123]])=== | + | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17828123. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828123]])=== |
| Line 1,480: | Line 1,457: | ||
| − | ===MEMORY DEVICES AND METHODS FOR OPERATING THE SAME ([[US Patent Application 17752580. MEMORY DEVICES AND METHODS FOR OPERATING THE SAME simplified abstract|17752580]])=== | + | ===MEMORY DEVICES AND METHODS FOR OPERATING THE SAME ([[US Patent Application 17752580. MEMORY DEVICES AND METHODS FOR OPERATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752580]])=== |
| Line 1,488: | Line 1,465: | ||
| − | ===MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT ([[US Patent Application 18447638. MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT simplified abstract|18447638]])=== | + | ===MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT ([[US Patent Application 18447638. MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447638]])=== |
| Line 1,496: | Line 1,473: | ||
| − | ===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18361249. SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18361249]])=== | + | ===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18361249. SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361249]])=== |
| Line 1,504: | Line 1,481: | ||
| − | ===MEMORY DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18446582. MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|18446582]])=== | + | ===MEMORY DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18446582. MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446582]])=== |
| Line 1,512: | Line 1,489: | ||
| − | ===FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 18181229. FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract|18181229]])=== | + | ===FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 18181229. FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18181229]])=== |
| Line 1,520: | Line 1,497: | ||
| − | ===MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18361548. MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18361548]])=== | + | ===MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18361548. MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361548]])=== |
| Line 1,528: | Line 1,505: | ||
| − | ===THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446894. THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18446894]])=== | + | ===THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446894. THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446894]])=== |
| Line 1,536: | Line 1,513: | ||
| − | ===SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME ([[US Patent Application 18358966. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract|18358966]])=== | + | ===SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME ([[US Patent Application 18358966. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358966]])=== |
| Line 1,544: | Line 1,521: | ||
| − | ===MEMORY CELL ISOLATION ([[US Patent Application 17826100. MEMORY CELL ISOLATION simplified abstract|17826100]])=== | + | ===MEMORY CELL ISOLATION ([[US Patent Application 17826100. MEMORY CELL ISOLATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826100]])=== |
| Line 1,552: | Line 1,529: | ||
| − | ===EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR ([[US Patent Application 18446557. EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR simplified abstract|18446557]])=== | + | ===EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR ([[US Patent Application 18446557. EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446557]])=== |
| Line 1,560: | Line 1,537: | ||
| − | ===METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 17825440. METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE simplified abstract|17825440]])=== | + | ===METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 17825440. METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825440]])=== |
| Line 1,568: | Line 1,545: | ||
| − | ===METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18448100. METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract|18448100]])=== | + | ===METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18448100. METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448100]])=== |
| Line 1,576: | Line 1,553: | ||
| − | ===SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION ([[US Patent Application 18232027. SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION simplified abstract|18232027]])=== | + | ===SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION ([[US Patent Application 18232027. SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232027]])=== |
| Line 1,584: | Line 1,561: | ||
| − | ===Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices ([[US Patent Application 18361677. Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices simplified abstract|18361677]])=== | + | ===Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices ([[US Patent Application 18361677. Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361677]])=== |
| Line 1,592: | Line 1,569: | ||
| − | ===MEMORY DEVICE AND METHOD OF FABRICATING THE SAME ([[US Patent Application 17827998. MEMORY DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract|17827998]])=== | + | ===MEMORY DEVICE AND METHOD OF FABRICATING THE SAME ([[US Patent Application 17827998. MEMORY DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827998]])=== |
| Line 1,600: | Line 1,577: | ||
| − | ===MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17900892. MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|17900892]])=== | + | ===MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17900892. MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17900892]])=== |
| Line 1,608: | Line 1,585: | ||
| − | ===SIDEWALL SPACER STRUCTURE FOR MEMORY CELL ([[US Patent Application 18364697. SIDEWALL SPACER STRUCTURE FOR MEMORY CELL simplified abstract|18364697]])=== | + | ===SIDEWALL SPACER STRUCTURE FOR MEMORY CELL ([[US Patent Application 18364697. SIDEWALL SPACER STRUCTURE FOR MEMORY CELL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364697]])=== |
| Line 1,616: | Line 1,593: | ||
| − | ===STRUCTURE AND METHOD FOR MRAM DEVICES ([[US Patent Application 18446563. STRUCTURE AND METHOD FOR MRAM DEVICES simplified abstract|18446563]])=== | + | ===STRUCTURE AND METHOD FOR MRAM DEVICES ([[US Patent Application 18446563. STRUCTURE AND METHOD FOR MRAM DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446563]])=== |
| Line 1,624: | Line 1,601: | ||
| − | ===MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT ([[US Patent Application 18358685. MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT simplified abstract|18358685]])=== | + | ===MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT ([[US Patent Application 18358685. MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358685]])=== |
| Line 1,632: | Line 1,609: | ||
| − | ===METHODS OF FORMING MEMORY DEVICES ([[US Patent Application 18363751. METHODS OF FORMING MEMORY DEVICES simplified abstract|18363751]])=== | + | ===METHODS OF FORMING MEMORY DEVICES ([[US Patent Application 18363751. METHODS OF FORMING MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363751]])=== |
Revision as of 07:02, 5 December 2023
Contents
- 1 Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023
- 1.1 PARTICLE REMOVER AND METHOD (18448963)
- 1.2 DEVICE FOR FORMING CONDUCTIVE POWDER (18447161)
- 1.3 POLISHING METROLOGY (17898163)
- 1.4 MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE (18364702)
- 1.5 MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE (18446741)
- 1.6 WIRE-BOND DAMPER FOR SHOCK ABSORPTION (18446740)
- 1.7 DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE (17825225)
- 1.8 SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL (18447543)
- 1.9 TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS (18150772)
- 1.10 TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS (18170401)
- 1.11 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE (18362983)
- 1.12 FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME (18448032)
- 1.13 METHOD OF MAKING PHOTONIC DEVICE (18448046)
- 1.14 METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING (18448095)
- 1.15 METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING (18358790)
- 1.16 PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF (18232674)
- 1.17 PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME (18362046)
- 1.18 PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE (18232264)
- 1.19 PHOTORESIST MATERIALS AND ASSOCIATED METHODS (18447568)
- 1.20 PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18232225)
- 1.21 PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232220)
- 1.22 UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232774)
- 1.23 PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN (18232717)
- 1.24 SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS (18365529)
- 1.25 METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR (18358904)
- 1.26 SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (18446870)
- 1.27 OPTIMIZED MASK STITCHING (18231070)
- 1.28 ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES (18232745)
- 1.29 MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW (18447361)
- 1.30 SEMICONDUCTOR WAFER COOLING (18362037)
- 1.31 MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME (18355222)
- 1.32 FAULT DIAGNOSTICS (18303219)
- 1.33 INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17821559)
- 1.34 METHOD FOR CHIP INTEGRATION (17828648)
- 1.35 SEMICONDUCTOR DEVICE (18361815)
- 1.36 ANTI-FUSE ARRAY (18446684)
- 1.37 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME (18446771)
- 1.38 METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS (18447964)
- 1.39 SILICON PHOTONICS SYSTEM (18155980)
- 1.40 INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (18354377)
- 1.41 TRANSMISSION GATE STRUCTURE (18362195)
- 1.42 SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT (18448143)
- 1.43 NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY (17824306)
- 1.44 MEMORY DEVICE WITH SOURCE LINE CONTROL (18232542)
- 1.45 Systems and Methods for Controlling Power Management Operations in a Memory Device (18446818)
- 1.46 ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES (18446072)
- 1.47 FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR (17826180)
- 1.48 MEMORY DEVICE WITH REDUCED AREA (17752662)
- 1.49 THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY (18232539)
- 1.50 NON-VOLATILE MEMORY CIRCUIT AND METHOD (18448152)
- 1.51 FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL (18447410)
- 1.52 DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING (18231165)
- 1.53 SEMICONDUCTOR TOOL FOR COPPER DEPOSITION (18447557)
- 1.54 METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS (18225576)
- 1.55 SEMICONDUCTOR DEVICE PRE-CLEANING (17804447)
- 1.56 APPARATUS FOR ELECTRO-CHEMICAL PLATING (18231196)
- 1.57 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (17829154)
- 1.58 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (18232758)
- 1.59 METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL (18447810)
- 1.60 NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL (18446652)
- 1.61 CHEMICAL DISPENSING SYSTEM (18447353)
- 1.62 SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE (18358517)
- 1.63 SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF (18446549)
- 1.64 ETCH METHOD FOR INTERCONNECT STRUCTURE (18447134)
- 1.65 LOCAL INTERCONNECT (18447549)
- 1.66 SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME (18230338)
- 1.67 METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES (17825307)
- 1.68 METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH (17825678)
- 1.69 GATE CONTACT STRUCTURE (18446326)
- 1.70 METAL GATE PROCESS AND RELATED STRUCTURE (17804146)
- 1.71 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION (18360814)
- 1.72 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE (18361501)
- 1.73 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18447125)
- 1.74 SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME (17824249)
- 1.75 REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES (18359747)
- 1.76 HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER (18447239)
- 1.77 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (17824263)
- 1.78 MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION (18359206)
- 1.79 SYSTEMS AND METHODS OF TESTING MEMORY DEVICES (18232518)
- 1.80 SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE (18232520)
- 1.81 MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE (18363742)
- 1.82 STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE (18446076)
- 1.83 SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING (18447927)
- 1.84 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (17827992)
- 1.85 INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME (17829243)
- 1.86 VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS (17825336)
- 1.87 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (18361917)
- 1.88 Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via (18447871)
- 1.89 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18359864)
- 1.90 SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH (18232523)
- 1.91 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18363766)
- 1.92 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446873)
- 1.93 BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE (18447722)
- 1.94 SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING (17825698)
- 1.95 SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD (17752704)
- 1.96 DIAGONAL VIA STRUCTURE (18448125)
- 1.97 SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT (18232306)
- 1.98 ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY (18446025)
- 1.99 FIRST METAL STRUCTURE, LAYOUT, AND METHOD (17752737)
- 1.100 POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS (18361666)
- 1.101 METHOD OF MANUFACTURING INTEGRATED CIRCUIT (18447572)
- 1.102 CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES (18448005)
- 1.103 METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS (18448028)
- 1.104 INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT (18360012)
- 1.105 INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS (17825345)
- 1.106 SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE (17825741)
- 1.107 SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF (17823063)
- 1.108 SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION (17824353)
- 1.109 SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME (18230999)
- 1.110 SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS (17824330)
- 1.111 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18361953)
- 1.112 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME (18447979)
- 1.113 SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME (17826604)
- 1.114 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18229682)
- 1.115 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18362862)
- 1.116 INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17828981)
- 1.117 LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE (18366831)
- 1.118 METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE (18360214)
- 1.119 IMAGE SENSOR WITH A HIGH ABSORPTION LAYER (18364662)
- 1.120 PIXEL SENSOR INCLUDING A TRANSFER FINFET (18447340)
- 1.121 EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR (18364667)
- 1.122 IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION (18446572)
- 1.123 METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY (18360966)
- 1.124 OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE (17824183)
- 1.125 BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR (18364682)
- 1.126 DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR (18364734)
- 1.127 INDUCTIVE DEVICE (18447482)
- 1.128 Resistor Structure (18358557)
- 1.129 A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE (18366156)
- 1.130 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17824436)
- 1.131 SUPER JUNCTION STRUCTURE (18448013)
- 1.132 NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION (18232545)
- 1.133 SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME (18366210)
- 1.134 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME (17824329)
- 1.135 GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME (17804751)
- 1.136 EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION (17824915)
- 1.137 INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE (18363077)
- 1.138 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF (17752211)
- 1.139 Semiconductor Gate-All-Around Device (18360080)
- 1.140 PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS (18361262)
- 1.141 SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER (18446864)
- 1.142 SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF (18360085)
- 1.143 SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION (18447344)
- 1.144 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES (17752461)
- 1.145 SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME (17825411)
- 1.146 SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF (18447183)
- 1.147 SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF (17804125)
- 1.148 Spacer Structures for Nano-Sheet-Based Devices (18446733)
- 1.149 3D CAPACITOR AND METHOD OF MANUFACTURING SAME (18366596)
- 1.150 GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE (17824690)
- 1.151 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17826174)
- 1.152 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE (18232289)
- 1.153 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18232544)
- 1.154 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447489)
- 1.155 INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE (18364679)
- 1.156 FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME (17827755)
- 1.157 METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE (18446539)
- 1.158 HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION (17804438)
- 1.159 ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS (18446664)
- 1.160 SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE (17824669)
- 1.161 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (17825516)
- 1.162 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18359690)
- 1.163 METHOD OF MAKING DECOUPLING CAPACITOR (18447194)
- 1.164 SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS (17827251)
- 1.165 DECOUPLING FINFET CAPACITORS (18358464)
- 1.166 VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING (18446031)
- 1.167 CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME (18362916)
- 1.168 DATA RETENTION CIRCUIT AND METHOD (18363192)
- 1.169 Flip Flop Circuit (18366981)
- 1.170 SYSTEM AND SEMICONDUCTOR DEVICE THEREIN (17828834)
- 1.171 POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION (17828581)
- 1.172 Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18446849)
- 1.173 Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18447372)
- 1.174 Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation (18446881)
- 1.175 Programmable Regulator Voltage Controlled Ring Oscillator (18366742)
- 1.176 Circuits and Methods for a Noise Shaping Analog To Digital Converter (18361949)
- 1.177 METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE (18361816)
- 1.178 EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY (18231017)
- 1.179 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17826225)
- 1.180 IC INCLUDING STANDARD CELLS AND SRAM CELLS (18361185)
- 1.181 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446094)
- 1.182 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17828123)
- 1.183 MEMORY DEVICES AND METHODS FOR OPERATING THE SAME (17752580)
- 1.184 MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT (18447638)
- 1.185 SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361249)
- 1.186 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18446582)
- 1.187 FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME (18181229)
- 1.188 MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361548)
- 1.189 THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18446894)
- 1.190 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18358966)
- 1.191 MEMORY CELL ISOLATION (17826100)
- 1.192 EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR (18446557)
- 1.193 METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE (17825440)
- 1.194 METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE (18448100)
- 1.195 SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION (18232027)
- 1.196 Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices (18361677)
- 1.197 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME (17827998)
- 1.198 MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (17900892)
- 1.199 SIDEWALL SPACER STRUCTURE FOR MEMORY CELL (18364697)
- 1.200 STRUCTURE AND METHOD FOR MRAM DEVICES (18446563)
- 1.201 MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT (18358685)
- 1.202 METHODS OF FORMING MEMORY DEVICES (18363751)
Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023
PARTICLE REMOVER AND METHOD (18448963)
Main Inventor
Wen-Hao Cheng
DEVICE FOR FORMING CONDUCTIVE POWDER (18447161)
Main Inventor
You-Hua CHOU
POLISHING METROLOGY (17898163)
Main Inventor
Chih Hung CHEN
MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE (18364702)
Main Inventor
Kuei-Sung Chang
MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE (18446741)
Main Inventor
Chun-Wen Cheng
WIRE-BOND DAMPER FOR SHOCK ABSORPTION (18446740)
Main Inventor
Tsung-Lin Hsieh
DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE (17825225)
Main Inventor
Wen-Chuan Tai
SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL (18447543)
Main Inventor
Yi-Lin WANG
TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS (18150772)
Main Inventor
Jaw-Juinn HORNG
TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS (18170401)
Main Inventor
Szu-Lin Liu
METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE (18362983)
Main Inventor
Feng-Wei KUO
FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME (18448032)
Main Inventor
Chen-Hao HUANG
METHOD OF MAKING PHOTONIC DEVICE (18448046)
Main Inventor
Chien-Ying WU
METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING (18448095)
Main Inventor
Sui-Ying HSU
METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING (18358790)
Main Inventor
Yu-Hao CHEN
PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF (18232674)
Main Inventor
Yun-Yue LIN
PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME (18362046)
Main Inventor
Kuo-Hao LEE
PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE (18232264)
Main Inventor
An-Ren ZI
PHOTORESIST MATERIALS AND ASSOCIATED METHODS (18447568)
Main Inventor
Ming-Hui WENG
PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18232225)
Main Inventor
An-Ren Zi
PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232220)
Main Inventor
Yen-Hao CHEN
UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232774)
Main Inventor
Ming-Hui WENG
PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN (18232717)
Main Inventor
An-Ren ZI
SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS (18365529)
Main Inventor
Wen-Zhan Zhou
METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR (18358904)
Main Inventor
Hung-Jui Kuo
SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (18446870)
Main Inventor
Kai-Chieh CHANG
OPTIMIZED MASK STITCHING (18231070)
Main Inventor
Sagar TRIVEDI
ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES (18232745)
Main Inventor
Yih-Chen SU
MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW (18447361)
Main Inventor
Chun-Kai CHANG
SEMICONDUCTOR WAFER COOLING (18362037)
Main Inventor
Yung-Yao LEE
MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME (18355222)
Main Inventor
Saman M. I. ADHAM
FAULT DIAGNOSTICS (18303219)
Main Inventor
Sandeep Kumar Goel
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17821559)
Main Inventor
Johnny Chiahao LI
METHOD FOR CHIP INTEGRATION (17828648)
Main Inventor
Yung Feng Chang
SEMICONDUCTOR DEVICE (18361815)
Main Inventor
Yu-Jen CHEN
ANTI-FUSE ARRAY (18446684)
Main Inventor
Meng-Sheng CHANG
INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME (18446771)
Main Inventor
Yu-Jung CHANG
METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS (18447964)
Main Inventor
Yen-Pin CHEN
SILICON PHOTONICS SYSTEM (18155980)
Main Inventor
Feng-Wei KUO
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (18354377)
Main Inventor
John LIN
TRANSMISSION GATE STRUCTURE (18362195)
Main Inventor
Shao-Lun CHIEN
SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT (18448143)
Main Inventor
Fong-Yuan CHANG
NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY (17824306)
Main Inventor
Chieh Lee
MEMORY DEVICE WITH SOURCE LINE CONTROL (18232542)
Main Inventor
Perng-Fei Yuh
Systems and Methods for Controlling Power Management Operations in a Memory Device (18446818)
Main Inventor
Sanjeev Kumar Jain
ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES (18446072)
Main Inventor
Chien-Yuan Chen
FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR (17826180)
Main Inventor
Elia Ambrosi
MEMORY DEVICE WITH REDUCED AREA (17752662)
Main Inventor
Chun-Ying Lee
THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY (18232539)
Main Inventor
Meng-Sheng Chang
NON-VOLATILE MEMORY CIRCUIT AND METHOD (18448152)
Main Inventor
Gu-Huan LI
FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL (18447410)
Main Inventor
Sheng-Chieh HUANG
DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING (18231165)
Main Inventor
Ming Che CHEN
SEMICONDUCTOR TOOL FOR COPPER DEPOSITION (18447557)
Main Inventor
Chia-Hung TSAI
METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS (18225576)
Main Inventor
Wei-Lin CHANG
SEMICONDUCTOR DEVICE PRE-CLEANING (17804447)
Main Inventor
Yi-Hsiang CHAO
APPARATUS FOR ELECTRO-CHEMICAL PLATING (18231196)
Main Inventor
Kuo-Lung HOU
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (17829154)
Main Inventor
Po-Han LIN
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (18232758)
Main Inventor
Chun-Wei LIAO
METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL (18447810)
Main Inventor
Yun-Jui HE
NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL (18446652)
Main Inventor
Ya-Wen Chiu
CHEMICAL DISPENSING SYSTEM (18447353)
Main Inventor
Ming-Chieh HSU
SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE (18358517)
Main Inventor
Yi-Fam Shiu
SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF (18446549)
Main Inventor
Soon-Kang HUANG
ETCH METHOD FOR INTERCONNECT STRUCTURE (18447134)
Main Inventor
Chun-Cheng Chou
LOCAL INTERCONNECT (18447549)
Main Inventor
Cheng-Hsien Wu
SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME (18230338)
Main Inventor
Ting-Ya LO
METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES (17825307)
Main Inventor
Yu-Chen KO
METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH (17825678)
Main Inventor
Chung-Liang CHENG
GATE CONTACT STRUCTURE (18446326)
Main Inventor
Cheng-Chi Chuang
METAL GATE PROCESS AND RELATED STRUCTURE (17804146)
Main Inventor
Chih-Lun LU
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION (18360814)
Main Inventor
Osamu KOIKE
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE (18361501)
Main Inventor
Chung-Ting KO
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18447125)
Main Inventor
Shu-Uei Jang
SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME (17824249)
Main Inventor
Ta-Chun LIN
REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES (18359747)
Main Inventor
Yu-Jen Shen
HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER (18447239)
Main Inventor
Huiching Chang
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (17824263)
Main Inventor
Chih-Hsin Yang
MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION (18359206)
Main Inventor
I-Che Lee
SYSTEMS AND METHODS OF TESTING MEMORY DEVICES (18232518)
Main Inventor
Meng-Han Lin
SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE (18232520)
Main Inventor
Tsung-Yang Hsieh
MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE (18363742)
Main Inventor
Meng-Liang Lin
STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE (18446076)
Main Inventor
Jen-Yuan CHANG
SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING (18447927)
Main Inventor
Jian WU
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (17827992)
Main Inventor
Wei-Ming Wang
INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME (17829243)
Main Inventor
Chang-Jung HSUEH
VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS (17825336)
Main Inventor
Ting-Yu Yeh
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (18361917)
Main Inventor
Jen-Chun Liao
Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via (18447871)
Main Inventor
Yung-Chi Lin
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18359864)
Main Inventor
Ting-Yu Yeh
SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH (18232523)
Main Inventor
Yueh-Ting Lin
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18363766)
Main Inventor
Chien-Hung Chen
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446873)
Main Inventor
Chung-Ting Lu
BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE (18447722)
Main Inventor
Tsung-Chieh Hsiao
SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING (17825698)
Main Inventor
Chih-Yu Lu
SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD (17752704)
Main Inventor
Chi-Yu LU
DIAGONAL VIA STRUCTURE (18448125)
Main Inventor
Shih-Wei PENG
SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT (18232306)
Main Inventor
Gerben DOORNBOS
ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY (18446025)
Main Inventor
Shih-Wei Peng
FIRST METAL STRUCTURE, LAYOUT, AND METHOD (17752737)
Main Inventor
Chi-Yu LU
POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS (18361666)
Main Inventor
Chih-Liang CHEN
METHOD OF MANUFACTURING INTEGRATED CIRCUIT (18447572)
Main Inventor
Chih-Yu LAI
CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES (18448005)
Main Inventor
Li-Chun Tien
METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS (18448028)
Main Inventor
Chih-Liang CHEN
INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT (18360012)
Main Inventor
Shin-Yi Yang
INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS (17825345)
Main Inventor
Chien Hung Liu
SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE (17825741)
Main Inventor
Hsi-Wen TIEN
SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF (17823063)
Main Inventor
Sheng-Fan YANG
SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION (17824353)
Main Inventor
Shu-Chun Yang
SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME (18230999)
Main Inventor
Cheng-Chieh HSIEH
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS (17824330)
Main Inventor
Fong-yuan Chang
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18361953)
Main Inventor
Chung-Liang CHENG
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME (18447979)
Main Inventor
Te-Hsin CHIU
SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME (17826604)
Main Inventor
Yi-Ruei JHAN
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18229682)
Main Inventor
Jui-Chien HUANG
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18362862)
Main Inventor
Yu-Lien HUANG
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17828981)
Main Inventor
Chin-Wei HSU
LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE (18366831)
Main Inventor
Harry-Hak-Lay Chuang
METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE (18360214)
Main Inventor
Ming Chyi Liu
IMAGE SENSOR WITH A HIGH ABSORPTION LAYER (18364662)
Main Inventor
Chien-Chang Huang
PIXEL SENSOR INCLUDING A TRANSFER FINFET (18447340)
Main Inventor
Feng-Chien HSIEH
EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR (18364667)
Main Inventor
Shih-Hsun Hsu
IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION (18446572)
Main Inventor
Hsiang-Lin Chen
METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY (18360966)
Main Inventor
Tsun-Kai Tsao
OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE (17824183)
Main Inventor
Yi-Hsien Chang
BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR (18364682)
Main Inventor
Cheng-Ta Wu
DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR (18364734)
Main Inventor
Feng-Chien HSIEH
INDUCTIVE DEVICE (18447482)
Main Inventor
Wei-Yu CHOU
Resistor Structure (18358557)
Main Inventor
Chih-Fan Huang
A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE (18366156)
Main Inventor
Szu-Hsien Lo
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17824436)
Main Inventor
Tsung-Chieh HSIAO
SUPER JUNCTION STRUCTURE (18448013)
Main Inventor
Shuai ZHANG
NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION (18232545)
Main Inventor
Lin-Chen Lu
SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME (18366210)
Main Inventor
Ko-Cheng Liu
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME (17824329)
Main Inventor
Lin-Yu HUANG
GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME (17804751)
Main Inventor
Chi-Ming CHEN
EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION (17824915)
Main Inventor
Chih Sheng Huang
INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE (18363077)
Main Inventor
Hsin Fu Lin
SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF (17752211)
Main Inventor
Jui-Lin CHANG
Semiconductor Gate-All-Around Device (18360080)
Main Inventor
Jhon Jhy Liaw
PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS (18361262)
Main Inventor
Meng-Huan Jao
SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER (18446864)
Main Inventor
Shih-Chuan Chiu
SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF (18360085)
Main Inventor
Po-Yu Huang
SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION (18447344)
Main Inventor
Te-Chih HSIUNG
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES (17752461)
Main Inventor
Yung-Hsiang CHAN
SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME (17825411)
Main Inventor
Shin-Yi YANG
SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF (18447183)
Main Inventor
Chih-Ching Wang
SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF (17804125)
Main Inventor
Wen-Shun LO
Spacer Structures for Nano-Sheet-Based Devices (18446733)
Main Inventor
Shih-Cheng Chen
3D CAPACITOR AND METHOD OF MANUFACTURING SAME (18366596)
Main Inventor
Chi-Wen LIU
GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE (17824690)
Main Inventor
Tien-Shun CHANG
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17826174)
Main Inventor
Wang-Chun Huang
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE (18232289)
Main Inventor
Chia-Chi YU
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18232544)
Main Inventor
Shih-Yao LIN
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447489)
Main Inventor
Wei-Chih KAO
INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE (18364679)
Main Inventor
Man-Ho Kwan
FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME (17827755)
Main Inventor
Gerben Doornbos
METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE (18446539)
Main Inventor
Eric PENG
HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION (17804438)
Main Inventor
Jhu-Min SONG
ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS (18446664)
Main Inventor
Shi Ning Ju
SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE (17824669)
Main Inventor
Hung-Yu YEN
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (17825516)
Main Inventor
Shuen-Shin LIANG
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18359690)
Main Inventor
Marcus Johannes Henricus VAN DAL
METHOD OF MAKING DECOUPLING CAPACITOR (18447194)
Main Inventor
Szu-Lin LIU
SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS (17827251)
Main Inventor
Po-Chia Lai
DECOUPLING FINFET CAPACITORS (18358464)
Main Inventor
Chung-Hui Chen
VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING (18446031)
Main Inventor
Chin-Ho Chang
CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME (18362916)
Main Inventor
Seid Hadi RASOULI
DATA RETENTION CIRCUIT AND METHOD (18363192)
Main Inventor
Kai-Chi HUANG
Flip Flop Circuit (18366981)
Main Inventor
Po-Chia Lai
SYSTEM AND SEMICONDUCTOR DEVICE THEREIN (17828834)
Main Inventor
Tsung-Che LU
POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION (17828581)
Main Inventor
Chin-Hua Wen
Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18446849)
Main Inventor
Jerrin Pathrose Vareed
Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18447372)
Main Inventor
Jerrin Pathrose Vareed
Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation (18446881)
Main Inventor
Tsung-Hsien Tsai
Programmable Regulator Voltage Controlled Ring Oscillator (18366742)
Main Inventor
Tsung-Hsien Tsai
Circuits and Methods for a Noise Shaping Analog To Digital Converter (18361949)
Main Inventor
Martin Kinyua
METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE (18361816)
Main Inventor
En-Hsiang YEH
EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY (18231017)
Main Inventor
Shang-Chieh CHIEN
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17826225)
Main Inventor
Chun-Hung CHEN
IC INCLUDING STANDARD CELLS AND SRAM CELLS (18361185)
Main Inventor
Jhon-Jhy LIAW
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446094)
Main Inventor
Shih-Yao Lin
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17828123)
Main Inventor
Jhon-Jhy LIAW
MEMORY DEVICES AND METHODS FOR OPERATING THE SAME (17752580)
Main Inventor
Hsiang-Wei Liu
MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT (18447638)
Main Inventor
Meng-Sheng CHANG
SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361249)
Main Inventor
Meng-Han Lin
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18446582)
Main Inventor
Feng-Ching Chu
FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME (18181229)
Main Inventor
Yi-Hsuan Chen
MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361548)
Main Inventor
Meng-Han Lin
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18446894)
Main Inventor
Meng-Han Lin
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18358966)
Main Inventor
Gerben Doornbos
MEMORY CELL ISOLATION (17826100)
Main Inventor
Tzu-Yu Chen
EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR (18446557)
Main Inventor
Kuan-Liang Liu
METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE (17825440)
Main Inventor
Wei-Chih WEN
METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE (18448100)
Main Inventor
Yu-Hao CHEN
SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION (18232027)
Main Inventor
Yi Yang
Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices (18361677)
Main Inventor
Yi Yang
MEMORY DEVICE AND METHOD OF FABRICATING THE SAME (17827998)
Main Inventor
Yen-Lin Huang
MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (17900892)
Main Inventor
Ming-Yuan Song
SIDEWALL SPACER STRUCTURE FOR MEMORY CELL (18364697)
Main Inventor
Yao-Wen Chang
STRUCTURE AND METHOD FOR MRAM DEVICES (18446563)
Main Inventor
Tsung-Chieh Hsiao
MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT (18358685)
Main Inventor
Hai-Dang TRINH
METHODS OF FORMING MEMORY DEVICES (18363751)
Main Inventor
Hung-Li Chiang
