Taiwan Semiconductor Manufacturing Co., Ltd. patent applications published on October 5th, 2023

Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on October 5th, 2023

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME (17812530)

Inventor Chen-Hua Yu

Brief explanation

The abstract describes a package that contains an encapsulant with two sides. Inside the encapsulant, there are two integrated circuit dies. On one side of the encapsulant, there is a first interposer that is connected to the integrated circuit dies both mechanically and electrically. On the other side of the encapsulant, there is a second interposer that is also connected to the integrated circuit dies both mechanically and electrically. The second interposer serves to connect the first integrated circuit die to the second integrated circuit die either optically or electrically.

Abstract

A package includes an encapsulant having a first side and a second side opposite to the first side, a first integrated circuit die and a second integrated circuit die embedded in the encapsulant, and a first interposer on the first side of the encapsulant. The first interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The package further includes a second interposer on the second side of the encapsulant. The second interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The second interposer optically or electrically couples the first integrated circuit die to the second integrated circuit die.

EXTREME ULTRAVIOLET MASK AND METHOD FOR FORMING THE SAME (17744567)

Inventor Yun-Yue LIN

Brief explanation

The abstract describes a photolithography mask, which is a tool used in the manufacturing of microchips. The mask consists of several layers, including a substrate, a reflective multilayer structure, an adhesion layer, a capping layer, and a patterned absorber layer. The capping layer is made of a non-crystalline conductive material.

Abstract

A photolithography mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. The capping layer includes a non-crystalline conductive material.

High-Density Memory Cells and Layouts Thereof (17664465)

Inventor Jen-Chieh Liu

Brief explanation

The abstract describes a device that has a write bit line and a read bit line in one direction, and a write word line and a read word line in a perpendicular direction. The device also includes a memory cell with a write transistor and a read transistor. The write transistor has a gate connected to the write word line, a source/drain connected to the write bit line, and another source/drain connected to a data storage node. The read transistor has a gate connected to the data storage node, a source/drain connected to the read bit line, and another source/drain connected to the read word line.

Abstract

A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.

WORK FUNCTION TUNING IN SEMICONDUCTOR DEVICES (17807513)

Inventor Hsin-Yi LEE

Brief explanation

The abstract describes a method for creating a semiconductor device that uses a metal layer with tantalum to prevent oxygen diffusion and improve the device's threshold voltage. The method involves creating a gate dielectric layer on a channel structure and then adding a metal layer with a specific work function on top. The gate dielectric layer consists of an interfacial layer and a high-k dielectric layer. The method also includes doping both the metal layer and the gate dielectric layer with tantalum.

Abstract

The present disclosure describes a method for forming a semiconductor device having a work function metal layer doped with tantalum to mitigate oxygen diffusion and improve device threshold voltage. The method includes forming a gate dielectric layer on a channel structure and forming a work function metal layer on the gate dielectric layer. The gate dielectric layer includes an interfacial layer on the channel structure and a high-k dielectric layer on the interfacial layer. The method further includes doping the work function metal layer and the gate dielectric layer with tantalum.

Varying Temperature Anneal for Film and Structures Formed Thereby (18332056)

Inventor Shu Ling Liao

Brief explanation

The abstract describes semiconductor device structures that include dielectric features and the methods used to form these features. The dielectric features are created through a process called ALD (Atomic Layer Deposition) followed by a temperature annealing process. These features have a high density, low carbon concentration, and a lower k-value, which is a measure of their capacitance efficiency. The dielectric features formed using this method have improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes.

Abstract

Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

Gate Structure Passivating Species Drive-In Method and Structure Formed Thereby (18330885)

Inventor Hsiao-Kuan Wei

Brief explanation

The abstract describes a method for forming a gate structure in a device, such as in a replacement gate process. The method involves several steps: 

1. A gate dielectric layer is formed over an active area on a substrate. 2. A dummy layer containing a passivating species, such as fluorine, is formed over the gate dielectric layer. 3. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. 4. The dummy layer is then removed. 5. Finally, a metal gate electrode is formed over the gate dielectric layer.

The key aspect of this method is that the gate dielectric layer contains the passivating species before the metal gate electrode is formed.

Abstract

Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Semiconductor Device and Methods of Forming the Same (17711885)

Inventor Bor Chiuan Hsieh

Brief explanation

The abstract describes a method of creating a semiconductor device. It involves several steps, including forming a source/drain region on a substrate, adding a layer of interlayer dielectric, creating a gate structure next to the source/drain region, and placing a gate mask over the gate structure. The gate mask is formed by etching part of the gate structure to create a recess, depositing a dielectric layer in the recess, etching part of the dielectric layer, depositing a semiconductor layer in the recess, and then making the semiconductor layer flat with the interlayer dielectric. In some cases, a gate spacer is also formed, and part of it is etched during the process.

Abstract

A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.

Integrated Circuit Package and Method of Forming Thereof (18329302)

Inventor Hsien-Wei Chen

Brief explanation

The abstract describes a method for creating an integrated circuit package. It involves attaching a first die to an interposer, which is a component that connects different parts of the circuit. The interposer has connectors for the first and second dies, and these connectors are covered by a layer of insulating material. The first die is connected to the first connector and the insulating layer, while the second connector is exposed by the first die. The method also includes recessing the insulating layer to expose the second connector and attaching a second die to the interposer, connecting it to the second connector.

Abstract

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

SYSTEMS AND METHODS FOR AUTOMATED PROCESSING PORTS (18206544)

Inventor Tsung-Sheng KUO

Brief explanation

The abstract describes a system that includes a semiconductor processing tool with a tool port, a processing port with an internal and external location, a robot that moves a die vessel between the internal processing port and the tool port, and an actuator that moves the die vessel between the internal processing port and the external processing port.

Abstract

In an embodiment, a system includes: a tool port of a semiconductor processing tool; a processing port with an internal processing port location and an external processing port location; a robot configured to move a die vessel between the internal processing port location and the tool port; and an actuator configured to move the die vessel between the internal processing port location and the external processing port location.

Metal Loss Prevention Using Implantation (18330466)

Inventor Li-Chieh Wu

Brief explanation

The abstract describes a method for creating conductive features in a layer of material without the need for additional layers. The method involves using an implant species in the material, which is concentrated near the top surface of the material and decreases towards the bottom surface. This allows for direct contact between the conductive feature and the material, without the need for adhesion or barrier layers.

Abstract

The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Semiconductor Device and Method of Manufacture (18331387)

Inventor Chun-Yen Peng

Brief explanation

The abstract describes a new type of high-k film for use in semiconductor devices. The film is made up of nano-crystallite regions suspended within an amorphous matrix layer. This design prevents the formation of grain boundaries, which can cause leakage and oxidation within the film. The film can be modified by implanting dopants and changing the crystal phase to alter its permittivity and ferroelectric properties.

Abstract

A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions maybe modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material.

Gate Structure of a Semiconductor Device and Method of Forming Same (18314200)

Inventor Shahaji B. More

Brief explanation

This abstract describes a semiconductor device and a method of forming it. The device includes a substrate and a gate structure that extends across different regions of the substrate. The gate structure consists of multiple layers, including gate dielectric layers, work function layers, and a barrier layer. The work function layers are in contact with each other and the barrier layer is located along the sidewall of one of the work function layers. The abstract does not provide any specific details about the purpose or application of the semiconductor device.

Abstract

A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer.

ETCHING APPARATUS AND METHOD (18328656)

Inventor Bo-Ting LIAO

Brief explanation

This abstract describes a method used in a plasma processing apparatus. The method involves creating a smaller inner chamber within the main process chamber. Gas is introduced into this inner chamber, and the flow of the gas is measured. The flow rate of the gas is then adjusted to a desired rate. The method allows for processing a wafer using the gas at the desired rate, without the need for the inner chamber.

Abstract

A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

High Efficiency Heat Dissipation Using Thermal Interface Material Film (18328387)

Inventor Chih-Hao Chen

Brief explanation

This abstract describes a method for creating a semiconductor structure. The method involves attaching a semiconductor device to a substrate and placing a pre-formed thermal interface material (TIM) film over the device. The TIM film extends beyond the device's sidewalls. A lid is then attached to the substrate, creating an enclosed space where the semiconductor device and TIM film are located. The TIM film makes contact with the lid.

Abstract

A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

DEVICE WITH BACKSIDE POWER RAIL AND METHOD (17882339)

Inventor Yun Ju FAN

Brief explanation

The abstract describes a device that consists of several components. These components include a stack of very small semiconductor structures, a gate structure that surrounds the semiconductor structures, a region called the source/drain region that is connected to the gate structure and the stack, a contact structure on the source/drain region, a layer of insulating material underneath the stack, and a structure called a via that connects the contact structure to the top surface of the insulating layer.

Abstract

A device includes a stack of semiconductor nanostructures, a gate structure wrapping around the semiconductor nanostructures, a source/drain region abutting the gate structure and the stack, a contact structure on the source/drain region, a backside dielectric layer under the stack, and a via structure extending from the contact structure to a top surface of the backside dielectric layer.

NON-DMSO STRIPPER FOR ADVANCE PACKAGE METAL PLATING PROCESS (17827415)

Inventor Tzu-Yang LIN

Brief explanation

This abstract describes a method for creating a semiconductor structure. The method involves applying a patterned layer of photoresist onto a substrate and then removing this layer using a specific photoresist stripping composition. This composition does not contain dimethyl sulfoxide. The photoresist stripping composition includes an organic alkaline compound, such as a primary, secondary, or tertiary amine, or a quaternary ammonium hydroxide or salt. It also contains an organic solvent, such as a glycol ether, glycol acetate, glycol, pyrrolidone, or a mixture of these solvents. Additionally, a polymer solubilizer is included in the composition.

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a patterned photoresist layer over a substrate and removing the patterned photoresist layer using a photoresist stripping composition that is free of dimethyl sulfoxide. The photoresist stripping composition includes an organic alkaline compound including at least one of a primary amine, secondary amine, a tertiary amine or a quaternary ammonium hydroxide or a salt thereof, an organic solvent selected from the group consisting of a glycol ether, a glycol acetate, a glycol, a pyrrolidone and mixtures thereof, and a polymer solubilizer.

Semiconductor Devices and Methods of Manufacture (17740618)

Inventor Chen-Yu Tsai

Brief explanation

The abstract describes semiconductor devices and their manufacturing methods. These devices involve the creation of metallization layers on a semiconductor substrate. A first pad is then formed over these layers. One or more passivation layers are deposited over the first pad. Finally, a first bond pad is created by forming a through via that goes through the passivation layers and partially through the first pad.

Abstract

Semiconductor devices and methods of manufacture are presented which form metallization layers over a semiconductor substrate; form a first pad over the metallization layers; deposit one or more passivation layers over the first pad; and form a first bond pad via through the one or more passivation layers and at least partially through the first pad.

PREVENTION OF METAL PAD CORROSION DUE TO EXPOSURE TO HALOGEN (18329128)

Inventor Chih-Fan Huang

Brief explanation

The abstract describes a method for creating semiconductor devices and integrated circuits. The method involves depositing layers of dielectric material and polymeric material over a metal pad on a workpiece. Openings are then formed in these layers to expose the metal pad. Finally, a bump feature is formed over the exposed metal pad.

Abstract

Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.

Multi-Bump Connection to Interconnect Structure and Manufacturing Method Thereof (18327252)

Inventor Tsung-Yen Lee

Brief explanation

The abstract describes a method for creating a component for packaging electronic devices. The method involves creating a layer of insulating material, shaping it to create an opening, and then adding a line of conductive material with a connection point and a curved path. The connection point is positioned above the insulating layer, and the curved path connects the connection point to a vertical offset point. Finally, a small bump of conductive material is added to the connection point.

Abstract

A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.

INTEGRATED CIRCUIT PACKAGES HAVING ADHESION LAYERS FOR THROUGH VIAS (18330616)

Inventor Hung-Chun Cho

Brief explanation

The abstract describes a device that includes a semiconductor die, a through via, an encapsulant, and an adhesion layer. The semiconductor die is made of semiconductor material, while the through via is made of metal. The encapsulant is a polymer resin that surrounds both the through via and the semiconductor die. The adhesion layer acts as a bond between the encapsulant and the through via, and it is made up of an adhesive compound that contains an aromatic compound and an amino group. The amino group is connected to the polymer resin of the encapsulant, while the aromatic compound is connected to the metal of the through via. The aromatic compound is chemically inert to the semiconductor material of the semiconductor die.

Abstract

In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

SEMICONDUCTOR DEVICE AND METHOD HAVING HIGH-KAPPA BONDING LAYER (18151160)

Inventor Che Chi SHIH

Brief explanation

This abstract describes a new method of improving the thermal conductivity of semiconductor devices using a high-kappa dielectric bonding layer. The method involves placing a first substrate, a semiconductor device layer, and frontside interconnect structures on top of each other. A bonding layer with high thermal conductivity is then added on top of the interconnect structures. Finally, a second substrate is placed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.

Abstract

Semiconductor devices and methods are provided which facilitate improved thermal conductivity using a high-kappa dielectric bonding layer. In at least one example, a device is provided that includes a first substrate. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. Frontside interconnect structure are disposed on the semiconductor device layer, and a bonding layer is disposed on the frontside interconnect structure. A second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.

SEMICONDUCTOR DEVICE AND METHOD (17656935)

Inventor Kai-Qiang Wen

Brief explanation

This abstract describes a method for creating a specific structure on a substrate. The method involves creating a fin that sticks out from the substrate and then introducing different types of dopants to form n-type and p-type regions in the fin. Gate structures are then formed over these regions. Epitaxial regions are also formed adjacent to the gate structures on the fin.

Abstract

A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.

INTEGRATED CIRCUIT (18331011)

Inventor Guo-Huei WU

Brief explanation

The abstract describes a method for organizing and connecting transistors in a cell. The cell has active areas that are separated from each other in one direction. There are two gates that cross the active areas in another direction. The first gate is shared by a first and second type of transistor, while the second gate is shared by a third and fourth type of transistor. There are also conductive lines arranged in three metal tracks that connect the terminals of the transistors. The method involves turning off the first transistor to disconnect its source/drain terminal from the source/drain terminal of the fourth transistor.

Abstract

A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gate s that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

SEMICONDUCTOR DEVICE (18329218)

Inventor Zong-Jie WU

Brief explanation

This abstract describes a semiconductor device that consists of two semiconductor structures. The first structure is made of silicon and the second structure is embedded within the first structure. The second structure has both convex and concave portions, which are located on at least one edge of the structure. The concave portion has a shape that can be a rectangle, trapezoid, inverted trapezoid, or parallelogram. The second structure is made of germanium, elements from group III or group V of the periodic table, or a combination of these materials. The top surface of the convex portion of the second structure is aligned with the top surface of the first structure.

Abstract

A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes silicon. The second semiconductor structure is embedded in the first semiconductor structure, in which the second semiconductor structure has at least one convex portion and at least one concave portion. The convex portion and the concave portion are on at least one edge of the second semiconductor structure, and a shape of the concave portion includes rectangle, trapezoid, inverted trapezoid, or parallelogram. The second semiconductor structure includes germanium, elements of group III or group V, or combinations thereof. The convex portion of the second semiconductor structure has a top surface substantially coplanar with a top surface of the first semiconductor structure.

ISOLATION STRUCTURES IN IMAGE SENSORS (17879556)

Inventor Cheng-Ying Ho

Brief explanation

The abstract describes an optical device that has isolation structures and a method for making it. The device includes a substrate with two surfaces, and radiation sensing devices and isolation structures are placed within the substrate. The first isolation structure has two surfaces and is located within the substrate. The second isolation structure, which consists of a metal structure surrounded by a dielectric layer, is placed on the first surface of the first isolation structure. This second isolation structure extends vertically over the substrate's first surface.

Abstract

An optical device with isolation structures and a method of fabricating the same are disclosed. The optical device includes a substrate having a first surface and a second surface opposite to the first surface, first and second radiation sensing devices disposed in the substrate, a first isolation structure disposed in the substrate. The first isolation structure has a first surface and a second surface opposite to the first surface. The optical device further includes a second isolation structure disposed in the substrate and on the first surface of the first isolation structure. The second isolation structure includes a metal structure and a dielectric layer surrounding the metal structure. The second isolation structure vertically extends over the first surface of the substrate.

Source/Drain Regions of Semiconductor Device and Methods of Forming the Same (17712965)

Inventor Yung-Chun Yang

Brief explanation

This abstract describes a device that has a nanostructure on a substrate, along with a source/drain region next to the nanostructure. The source/drain region consists of two epitaxial layers, with the first layer covering one side of the nanostructure and having a specific concentration of a dopant. This first layer has a rounded convex shape opposite the nanostructure. The second layer covers the rounded convex shape of the first layer and has a different concentration of the same dopant.

Abstract

A device includes a first nanostructure over a substrate and a first source/drain region adjacent the first nanostructure. The first source/drain region includes a first epitaxial layer covering a first sidewall of the first nanostructure. The first epitaxial layer has a first concentration of a first dopant. The first epitaxial layer has a round convex profile opposite the first sidewall of the first nanostructure in a cross-sectional view. The first source/drain region further includes a second epitaxial layer covering the round convex profile of the first epitaxial layer in the cross-sectional view. The second epitaxial layer has a second concentration of the first dopant, the second concentration being different from the first concentration.

Semiconductor Device having Doped Gate Dielectric Layer and Method for Forming the Same (18152601)

Inventor Yao-Teng Chuang

Brief explanation

The abstract describes a semiconductor device that includes two layers of gate dielectric material, each doped with a dipole dopant. The first layer has a higher concentration of the dopant and a deeper concentration peak compared to the second layer. The device also has two gate electrodes with the same width, one over each layer of gate dielectric material.

Abstract

In an embodiment, a semiconductor device is provided, which includes a first doped gate dielectric layer and a second doped gate dielectric layer, wherein the first doped gate dielectric layer and the second doped gate dielectric layer comprise a high-k material doped with a dipole dopant. The second doped gate dielectric layer has a second concentration of the first dipole dopant. The concentration of the dipole dopant in the first doped gate dielectric layer is greater than the concentration, and the concentration peak of the dipole dopant in the first doped gate dielectric layer is deeper than the concentration peak of the dipole dopant in the second doped gate dielectric layer. A first gate electrode over the first doped gate dielectric layer, and a second gate electrode over the second doped gate dielectric layer, the first gate electrode and the second gate electrode have a same width.

SEMICONDUCTOR DEVICE WITH GATE DIELECTRIC FORMED USING SELECTIVE DEPOSITION (18324636)

Inventor Tung-Ying LEE

Brief explanation

This abstract describes a semiconductor device that consists of multiple layers of semiconductor material stacked on top of each other. On either side of these layers, there are regions called source/drain epitaxial regions. The device also includes a gate structure that surrounds each of the semiconductor layers. This gate structure is made up of interfacial layers, a high-k dielectric layer, and a gate metal. Additionally, there are gate spacers that separate the gate structure from the source/drain epitaxial regions. The important point to note is that the top position of the high-k dielectric layer is lower than the top positions of the gate spacers.

Abstract

A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

Gate Capping Structures In Semiconductor Devices (18206831)

Inventor Chung-Liang CHENG

Brief explanation

This abstract describes a semiconductor device and the methods used to create it. The device includes a substrate, a fin structure, a source/drain region, and a gate structure. The gate structure consists of a gate stack and a gate capping structure. The gate capping structure is made up of a conductive gate cap and an insulating gate cap. The device also includes a first contact structure that is located over the gate stack. A portion of the first contact structure is within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

Abstract

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

TRANSISTOR GATE STRUCTURES AND METHODS OF FORMING THEREOF (17833348)

Inventor Hsin-Yi Lee

Brief explanation

This abstract describes a device that includes a semiconductor substrate and a vertically stacked set of nanostructures on top of the substrate. The device also has a first source/drain region and a second source/drain region, with the nanostructures extending between them. The device further includes a gate structure that surrounds the nanostructures. The gate structure consists of a gate dielectric layer, a first metal carbide layer, and a gate fill material. The first metal carbide layer can be made of Ce, Hf, V, Nb, Sc, or Y.

Abstract

A device includes a semiconductor substrate; a vertically stacked set of nanostructures over the semiconductor substrate; a first source/drain region; and a second source/drain region, wherein the vertically stacked set of nanostructures extends between the first source/drain region and the second source/drain region along a first cross-section. The device further includes a gate structure encasing the vertically stacked set of nanostructures along a second cross-section. The second cross-section is along a longitudinal axis of the gate structure. The gate structure comprises: a gate dielectric encasing each of the vertically stacked set of nanostructures; a first metal carbide layer over the gate dielectric; and a gate fill material over the first metal carbide layer. The first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or

VOLTAGE SUPPLY SELECTION CIRCUIT (18330492)

Inventor Chia-Chen KUO

Brief explanation

This abstract describes a circuit that is used to select between two different voltage supplies. The circuit includes switches and control switches that receive control signals and voltage supplies. These switches are configured to selectively output the voltage supplies based on the control signal.

Abstract

The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

Phase-Change Memory and Method of Forming Same (18321843)

Inventor Jau-Yi Wu

Brief explanation

The abstract describes a device and a method for creating the device. The device consists of several layers, including a substrate, a first dielectric layer, a bottom electrode, a first buffer layer, a phase-change layer, a top electrode, and a second dielectric layer. The top electrode is wider than the bottom electrode. The purpose and specific details of the device are not provided in the abstract.

Abstract

A device and a method of forming the same are provided. The device includes a substrate, a first dielectric layer over the substrate, a bottom electrode extending through the first dielectric layer, a first buffer layer over the bottom electrode, a phase-change layer over the first buffer layer, a top electrode over the phase-change layer, and a second dielectric layer over the first dielectric layer. The second dielectric layer surrounds the phase-change layer and the top electrode. A width of the top electrode is greater than a width of the bottom electrode.