|
|
| (29 intermediate revisions by the same user not shown) |
| Line 28: |
Line 28: |
| | ==Patent applications for TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. on November 30th, 2023== | | ==Patent applications for TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. on November 30th, 2023== |
| | | | |
| − | ===APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824930. APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract|17824930]])=== | + | ===APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824930. APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824930]])=== |
| | | | |
| | | | |
| Line 36: |
Line 36: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18359900. METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18359900]])=== |
| − | The patent application describes an apparatus and method for forming a semiconductor structure.
| |
| − | * The apparatus includes a polishing pad, a polishing head, and a temperature control module.
| |
| − | * The polishing head holds a substrate against the polishing pad.
| |
| − | * The temperature control module is positioned facing the polishing pad.
| |
| − | * The temperature control module consists of a first temperature controller and a second temperature controller.
| |
| − | * The first temperature controller regulates the temperature of a first zone on the polishing pad.
| |
| − | * The second temperature controller regulates the temperature of a second zone on the polishing pad.
| |
| | | | |
| − | '''Abstract'''
| |
| − | An apparatus and a method for forming a semiconductor structure are provided. The apparatus includes a polishing pad, a polishing head and a temperature control module. The polishing head mounts a substrate against the polishing pad. The temperature control module faces the polishing pad. The temperature control module includes a first temperature controller and a second temperature controller. The first temperature controller is configured to control a first temperature of a first zone of the polishing pad. The second temperature controller is configured to control a second temperature of a second zone of the polishing pad.
| |
| | | | |
| − | ===METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18359900. METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract|18359900]])=== | + | '''Main Inventor''' |
| | + | |
| | + | YI-CHUAN TENG |
| | + | |
| | + | |
| | + | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME ([[US Patent Application 18359892. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18359892]])=== |
| | | | |
| | | | |
| | '''Main Inventor''' | | '''Main Inventor''' |
| | | | |
| − | YI-CHUAN TENG
| + | CHING-KAI SHEN |
| | + | |
| | + | |
| | + | ===ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION ([[US Patent Application 17827834. ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17827834]])=== |
| | + | |
| | | | |
| | + | '''Main Inventor''' |
| | | | |
| − | '''Brief explanation'''
| + | CHIA-CHUN LIAO |
| − | The patent application describes a method for manufacturing a semiconductor structure.
| |
| − | * A first substrate with a top surface is received.
| |
| − | * A semiconductor layer is formed over the first substrate.
| |
| − | * A cavity is formed at the top surface of the semiconductor layer.
| |
| − | * A second substrate is bonded over the first substrate to cover the semiconductor layer.
| |
| − | * The second substrate has a through hole connected to the cavity of the semiconductor layer.
| |
| − | * A eutectic sealing structure is formed on the second substrate to cover the through hole.
| |
| − | * The eutectic sealing structure includes a first metal layer and a second metal layer eutectically bonded on the first metal layer.
| |
| | | | |
| − | '''Abstract'''
| |
| − | A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A first substrate having a top surface is received. A semiconductor layer is formed over the first substrate. A cavity is formed at the top surface of the semiconductor layer. A second substrate is bonded over the first substrate to cover the semiconductor layer. The second substrate has a through hole connected to the cavity of the semiconductor layer. A eutectic sealing structure is formed on the second substrate to cover the through hole. The eutectic sealing structure includes a first metal layer and a second metal layer eutectically bonded on the first metal layer.
| |
| | | | |
| − | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME ([[US Patent Application 18359892. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME simplified abstract|18359892]])=== | + | ===VERTICAL POLARIZING BEAMSPLITTER FOR PHOTONICS ([[US Patent Application 17751777. VERTICAL POLARIZING BEAMSPLITTER FOR PHOTONICS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17751777]])=== |
| | | | |
| | | | |
| | '''Main Inventor''' | | '''Main Inventor''' |
| | | | |
| − | CHING-KAI SHEN
| + | Tai-Chun Huang |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===VERTICAL GRATING COUPLER ([[US Patent Application 17751773. VERTICAL GRATING COUPLER simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17751773]])=== |
| − | The patent application describes a method for fabricating a semiconductor structure.
| |
| − | * The method involves bonding a capping substrate over a sensing substrate.
| |
| − | * A through hole is formed in the capping substrate.
| |
| − | * A dielectric layer is formed over the capping substrate under a first vacuum level.
| |
| − | * A metal layer is formed over the dielectric layer under a second vacuum level.
| |
| − | * The second vacuum level is higher than the first vacuum level.
| |
| | | | |
| − | '''Abstract'''
| |
| − | The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.
| |
| | | | |
| − | ===ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION ([[US Patent Application 17827834. ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION simplified abstract|17827834]])===
| + | '''Main Inventor''' |
| | | | |
| | + | Tai-Chun Huang |
| | | | |
| − | '''Main Inventor'''
| |
| | | | |
| − | CHIA-CHUN LIAO
| + | ===VERTICAL GRATING FILTERS FOR PHOTONICS ([[US Patent Application 17751787. VERTICAL GRATING FILTERS FOR PHOTONICS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17751787]])=== |
| | + | |
| | | | |
| | + | '''Main Inventor''' |
| | | | |
| − | '''Brief explanation'''
| + | Tai-Chun Huang |
| − | - The patent application describes an electronic circuit and a method of error correction.
| |
| − | - The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit.
| |
| − | - The TDC generates a first signal.
| |
| − | - The error cancelation circuit evaluates a majority of bit values of at least a portion of the first signal to generate a second signal.
| |
| − | - The second signal has fewer transitions than the first signal.
| |
| − | - The purpose of the invention is to reduce errors in electronic circuits by minimizing the number of transitions in the signals generated by the TDC.
| |
| | | | |
| − | '''Abstract'''
| |
| − | An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.
| |
| | | | |
| − | ===EUV PHOTOMASK AND MANUFACTURING METHOD OF THE SAME ([[US Patent Application 18361891. EUV PHOTOMASK AND MANUFACTURING METHOD OF THE SAME simplified abstract|18361891]])=== | + | ===EUV PHOTOMASK AND MANUFACTURING METHOD OF THE SAME ([[US Patent Application 18361891. EUV PHOTOMASK AND MANUFACTURING METHOD OF THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18361891]])=== |
| | | | |
| | | | |
| Line 115: |
Line 92: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===METHOD AND SYSTEM FOR SCANNING WAFER ([[US Patent Application 18359871. METHOD AND SYSTEM FOR SCANNING WAFER simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18359871]])=== |
| − | - The patent application describes a photomask and a method of manufacturing it.
| |
| − | - The method involves several steps, including providing a substrate.
| |
| − | - A reflective layer is then deposited over the substrate, which includes molybdenum layers and silicon layers.
| |
| − | - A capping layer is deposited over the reflective layer.
| |
| − | - An absorption layer is then deposited over the capping layer.
| |
| − | - Finally, a treatment is performed to form a border region in the reflective layer, which includes molybdenum silicide.
| |
| − | - The purpose of this innovation is to improve the functionality and performance of photomasks used in various industries, such as semiconductor manufacturing.
| |
| − | | |
| − | '''Abstract'''
| |
| − | A photomask and a method of manufacturing a photomask are provided. According to an embodiment, a method includes: providing a substrate; depositing a reflective layer including molybdenum layers and silicon layers over the substrate; depositing a capping layer over the reflective layer; depositing an absorption layer over the capping layer; and performing a treatment to form a border region including molybdenum silicide in the reflective layer.
| |
| − | | |
| − | ===METHOD AND SYSTEM FOR SCANNING WAFER ([[US Patent Application 18359871. METHOD AND SYSTEM FOR SCANNING WAFER simplified abstract|18359871]])=== | |
| | | | |
| | | | |
| Line 135: |
Line 100: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===WET PROCESSING SYSTEM AND SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824926. WET PROCESSING SYSTEM AND SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824926]])=== |
| − | The patent application describes a method and system for scanning wafers.
| |
| − | * The system captures an image of a defect on a wafer.
| |
| − | * It generates a reference image using a reference image generation model.
| |
| − | * The system then creates a defect marked image by combining the defect image and the reference image.
| |
| − | | |
| − | '''Abstract'''
| |
| − | The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.
| |
| − | | |
| − | ===WET PROCESSING SYSTEM AND SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824926. WET PROCESSING SYSTEM AND SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract|17824926]])=== | |
| | | | |
| | | | |
| Line 152: |
Line 108: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE ([[US Patent Application 17752976. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17752976]])=== |
| − | The patent application describes a semiconductor structure manufacturing system.
| |
| − | * The system includes a load lock chamber, first chambers, second chambers, and a first robot.
| |
| − | * The load lock chamber is used to store wafers that need to be processed.
| |
| − | * The first chambers are responsible for processing the wafers and each has first stage plates to support the wafers.
| |
| − | * The second chambers are designed to process a single wafer and have a second stage plate for support.
| |
| − | * The first robot is responsible for transporting the wafers from the load lock chamber to the first chambers.
| |
| − | * The first robot is positioned between the first chambers, second chambers, and load lock chamber.
| |
| − | | |
| − | '''Abstract'''
| |
| − | A semiconductor structure manufacturing system is provided. The system includes a load lock chamber, first chambers, second chambers and a first robot. The load lock chamber is configured to store wafers that are to be processed. The first chambers are configured to process the wafers. Each of the first chambers has first stage plates for supporting the wafers. The second chambers are configured to process a single wafer. Each of the second chambers has a second stage plate for supporting a wafer. The first robot is configured to transport the wafers from the load lock chamber to the first chambers. The first robot is arranged between the first chambers, the second chambers and the load lock chamber.
| |
| − | | |
| − | ===METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM ([[US Patent Application 17824942. METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM simplified abstract|17824942]])=== | |
| | | | |
| | | | |
| | '''Main Inventor''' | | '''Main Inventor''' |
| | | | |
| − | YUAN-CHENG YANG
| + | You-Ru Lin |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM ([[US Patent Application 17824942. METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824942]])=== |
| − | The patent application describes a method for fabricating a transistor on a substrate. Here is a simplified explanation of the abstract:
| |
| | | | |
| − | * The method begins by etching a trench on the substrate's surface.
| |
| − | * The trench is then filled with a dielectric material to create a first isolation region.
| |
| − | * A patterned mask layer is deposited on the substrate, with an opening that exposes the substrate.
| |
| − | * Oxygen is implanted into the substrate through the opening, forming an implant region.
| |
| − | * The implant region is used to generate a second isolation region.
| |
| − | * Finally, a transistor is formed on the substrate, with a channel that surrounds the second isolation region.
| |
| | | | |
| − | Bullet points explaining the patent/innovation:
| + | '''Main Inventor''' |
| | | | |
| − | * The method involves creating isolation regions on a substrate to electrically separate different components.
| + | YUAN-CHENG YANG |
| − | * The use of a trench and a dielectric material helps in creating the first isolation region.
| |
| − | * Implanting oxygen into the substrate through a patterned mask layer allows for the formation of the second isolation region.
| |
| − | * The second isolation region is used to surround the channel of the transistor, providing electrical isolation.
| |
| − | * This method enables the fabrication of transistors with improved performance and reliability.
| |
| | | | |
| − | '''Abstract'''
| |
| − | A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.
| |
| | | | |
| − | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824936. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract|17824936]])=== | + | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824936. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824936]])=== |
| | | | |
| | | | |
| Line 201: |
Line 132: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 18360855. SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18360855]])=== |
| − | The patent application describes a semiconductor structure with two FET devices on a substrate.
| |
| − | * The substrate is divided into two regions, with one FET device in each region.
| |
| − | * The first FET device has a first isolation structure, a first gate electrode, and a first gate dielectric layer with a certain thickness.
| |
| − | * The second FET device has multiple fin structures, second isolation structures, a second gate electrode, and a second gate dielectric layer with a smaller thickness than the first.
| |
| − | * The innovation lies in the difference in gate dielectric layer thickness between the two FET devices.
| |
| − | | |
| − | '''Abstract'''
| |
| − | A semiconductor structure includes a substrate, a first FET device and a second FET device. The substrate has a first region and a second region. The first FET device is in the first region, and the second FET device is in the second region. The first FET device includes a first isolation structure, a first gate electrode disposed over a portion of the first isolation structure, and a first gate dielectric layer between the substrate and the first gate electrode. The first gate dielectric layer has a first thickness. The second FET device includes a plurality of fin structures, a plurality of second isolation structures, a second gate electrode over the plurality of fin structures, and a second gate dielectric layer between the second gate electrode and the plurality of fin structures. The second gate dielectric layer has a second thickness. The second thickness is less than the first thickness.
| |
| − | | |
| − | ===SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 18360855. SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME simplified abstract|18360855]])=== | |
| | | | |
| | | | |
| Line 219: |
Line 140: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824922. SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824922]])=== |
| − | The patent application describes a semiconductor structure with a fin protruding from a substrate.
| |
| − | * The fin consists of multiple layers of semiconductive material and a dielectric layer.
| |
| − | * The structure also includes a gate electrode with two conductive portions.
| |
| − | * The first conductive portion extends along the sidewalls of the first semiconductive layer and the upper surface of the substrate.
| |
| − | * The second conductive portion is isolated from the first conductive portion and extends along the sidewalls of the second semiconductive layer and the upper surface of the fin.
| |
| − | | |
| − | '''Abstract'''
| |
| − | A semiconductor structure includes: a substrate and a fin protruding from the substrate. The fin comprises a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure further includes a gate electrode including: a first conductive portion extending along two opposite sidewalls of the first semiconductive layer and along an upper surface of the substrate; and a second conductive portion electrically isolated from the first conductive portion and extending along two opposite sidewalls of the second semiconductive layer and along an upper surface of the fin.
| |
| − | | |
| − | ===SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824922. SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME simplified abstract|17824922]])=== | |
| | | | |
| | | | |
| Line 237: |
Line 148: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824924. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824924]])=== |
| − | The present disclosure describes a method of manufacturing a semiconductor structure for a CMOS image sensor.
| |
| − | | |
| − | * The method starts by providing a substrate and growing an epitaxial layer on it.
| |
| − | * A barrier layer is then formed on the epitaxial layer.
| |
| − | * A trench is formed in the epitaxial layer, and the epitaxial layer is oxidized to form a liner layer.
| |
| − | * A region for a photodiode is defined, and dopants are implanted around the trench to form a protective layer with a reduced thickness compared to the photodiode region.
| |
| − | * An oxide layer is formed in the trench, and an annealing operation is performed to densify the oxide layer, while keeping the protective layer spaced from the photodiode region.
| |
| − | * Finally, the photodiode is formed in the defined region.
| |
| − | | |
| − | This method allows for the manufacturing of a CMOS image sensor with improved performance and reliability.
| |
| − | | |
| − | '''Abstract'''
| |
| − | The present disclosure provides a method of manufacturing a semiconductor structure of a CMOS image sensor. The method includes providing a substrate; growing an epitaxial layer on the substrate; forming a barrier layer on the epitaxial layer; forming a trench extending into the epitaxial layer; oxidizing the epitaxial layer to form a liner layer; defining a region of a photodiode and a first dopant thickness; implanting dopants into the epitaxial layer around a sidewall of the trench to form a protective layer with a second dopant thickness less than the first dopant thickness; forming an oxide layer in the trench; performing an annealing operation to densify the oxide layer to form a densified oxide layer, wherein the protective layer, expanded from the second dopant thickness to a third dopant thickness less than the first dopant thickness, is kept spaced from the region; and forming the photodiode in the region.
| |
| − | | |
| − | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824924. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract|17824924]])=== | |
| | | | |
| | | | |
| Line 260: |
Line 156: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===MULTILAYER STRUCTURE, CAPACITOR STRUCTURE AND ELECTRONIC DEVICE ([[US Patent Application 17827837. MULTILAYER STRUCTURE, CAPACITOR STRUCTURE AND ELECTRONIC DEVICE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17827837]])=== |
| − | The patent application describes a semiconductor structure with a capacitor structure and a contact structure.
| |
| − | * The capacitor structure consists of an electrode layer, a protective dielectric layer, and a capacitor dielectric layer.
| |
| − | * The protective dielectric layer covers the top surface of the electrode layer.
| |
| − | * The capacitor dielectric layer is located on top of the protective oxide layer.
| |
| − | * The contact structure penetrates the protective oxide layer and establishes an electrical connection with the electrode layer.
| |
| − | | |
| − | '''Abstract'''
| |
| − | A semiconductor structure includes a capacitor structure and a contact structure. The capacitor structure includes an electrode layer, a protective dielectric layer, and a capacitor dielectric layer. The protective dielectric layer covers a top surface of the electrode layer. The capacitor dielectric layer is on the protective oxide layer. The contact structure penetrates the protective oxide layer and electrically connects to the electrode layer.
| |
| − | | |
| − | ===MULTILAYER STRUCTURE, CAPACITOR STRUCTURE AND ELECTRONIC DEVICE ([[US Patent Application 17827837. MULTILAYER STRUCTURE, CAPACITOR STRUCTURE AND ELECTRONIC DEVICE simplified abstract|17827837]])=== | |
| | | | |
| | | | |
| Line 278: |
Line 164: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===HIGH VOLTAGE DEVICE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17827824. HIGH VOLTAGE DEVICE AND METHOD FOR FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17827824]])=== |
| − | The patent application describes a multilayer structure, capacitor structure, and electronic device.
| |
| − | * The multilayer structure consists of three dielectric layers: a first dielectric layer, a second dielectric layer, and an intermediate dielectric layer.
| |
| − | * The intermediate dielectric layer is located between the first and second dielectric layers.
| |
| − | * The material of the intermediate dielectric layer is represented by the formula ABO, where A can be hafnium, zirconium, lanthanum, or tantalum, and B can be lanthanum, aluminum, or tantalum.
| |
| − | * A and B are different elements, and O represents oxygen.
| |
| − | * The value of x in the formula is a number between 0 and 1.
| |
| − | * The patent application aims to provide a multilayer structure with improved dielectric properties for use in electronic devices.
| |
| − | | |
| − | '''Abstract'''
| |
| − | A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of ABO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.
| |
| − | | |
| − | ===HIGH VOLTAGE DEVICE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17827824. HIGH VOLTAGE DEVICE AND METHOD FOR FORMING THE SAME simplified abstract|17827824]])=== | |
| | | | |
| | | | |
| Line 298: |
Line 172: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===METHODS FOR DOPING SEMICONDUCTORS IN TRANSISTORS ([[US Patent Application 17826298. METHODS FOR DOPING SEMICONDUCTORS IN TRANSISTORS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17826298]])=== |
| − | The abstract describes a high-voltage device with specific structural features and doping configurations. Here are the key points:
| + | |
| | | | |
| − | * The device consists of a substrate, a gate structure, a drain region, multiple source regions, and multiple doped regions.
| + | '''Main Inventor''' |
| − | * The gate structure is made up of alternating first and second portions, with the first portions being wider than the second portions.
| |
| − | * The source regions are located next to the first portions of the gate structure, while the doped regions are located next to the second portions.
| |
| − | * The drain region and source regions are doped with a certain type of conductivity, while the doped regions have a complementary type of conductivity.
| |
| − | * The purpose of this configuration is to enhance the performance and functionality of the high-voltage device.
| |
| | | | |
| − | '''Abstract'''
| + | Po-Hsun Ho |
| − | A high-voltage device includes a substrate, a gate structure over the substrate, a drain region disposed on a first side of the gate structure, a plurality of source regions disposed on a second side of the gate structure, and a plurality of doped regions disposed on the second side of the gate structure. The gate structure includes a plurality of first portions and a plurality of second portions alternately arranged. Width of the first portions are greater than widths of the second portions. The source regions are adjacent to the first portions of the gate structures, and the doped regions are adjacent to the second portions of the gate structure. The drain region and the source regions include dopants of a first conductivity type, and the doped regions include dopants of a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.
| |
| | | | |
| − | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18232533. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18232533]])=== | + | |
| | + | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18232533. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18232533]])=== |
| | | | |
| | | | |
| Line 318: |
Line 188: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===HIGH-ELECTRON-MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING ([[US Patent Application 17752970. HIGH-ELECTRON-MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17752970]])=== |
| − | The patent application describes a method for fabricating a semiconductor device.
| |
| − | * A plurality of semiconductor fins is formed in a first region on a substrate.
| |
| − | * An isolation region is formed around the semiconductor fins.
| |
| − | * Dummy fins are formed above the isolation region and adjacent to the semiconductor fins.
| |
| − | * The semiconductor fins are etched to have the same height as the isolation region.
| |
| − | * The isolation region is selectively etched to create a recess next to the semiconductor fins.
| |
| − | * The semiconductor fins are further etched to remove them and create a recess in the substrate.
| |
| | | | |
| − | '''Abstract'''
| |
| − | A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.
| |
| | | | |
| − | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTURE ([[US Patent Application 18360804. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTURE simplified abstract|18360804]])=== | + | '''Main Inventor''' |
| | + | |
| | + | Pravanshu Mohanta |
| | + | |
| | + | |
| | + | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTURE ([[US Patent Application 18360804. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18360804]])=== |
| | | | |
| | | | |
| Line 338: |
Line 204: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT DEVICE THEREOF ([[US Patent Application 17824923. METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT DEVICE THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824923]])=== |
| − | The present disclosure describes a semiconductor device and a method for fabricating it.
| |
| − | * The semiconductor device includes a substrate, a metal gate layer, a channel, and a ferroelectric layer.
| |
| − | * The ferroelectric layer is located between the metal gate layer and the substrate.
| |
| − | * The ferroelectric layer is made of a hafnium oxide-based material.
| |
| − | * The hafnium oxide-based material consists of three portions with different phases: orthorhombic, monoclinic, and tetragonal.
| |
| − | * The first portion of hafnium oxide with orthorhombic phase has a larger volume than the second portion with monoclinic phase.
| |
| − | * The second portion with monoclinic phase has a larger volume than the third portion with tetragonal phase.
| |
| | | | |
| − | '''Abstract'''
| |
| − | The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.
| |
| | | | |
| − | ===METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT DEVICE THEREOF ([[US Patent Application 17824923. METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT DEVICE THEREOF simplified abstract|17824923]])===
| + | '''Main Inventor''' |
| | | | |
| | + | WEI-KANG LIU |
| | | | |
| − | '''Main Inventor'''
| |
| | | | |
| − | WEI-KANG LIU
| + | ===HIGH-IMPLANT CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 18227236. HIGH-IMPLANT CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18227236]])=== |
| | + | |
| | | | |
| | + | '''Main Inventor''' |
| | | | |
| − | '''Brief explanation'''
| + | Chia-Chung CHEN |
| − | The patent application describes a method for manufacturing an integrated circuit device.
| |
| − | * The method involves using a photonic structure that includes an insulating structure and an optical coupler embedded within it.
| |
| − | * A portion of the insulating structure is removed to expose a coupling surface of the optical coupler.
| |
| − | * This removal forms a light reflective structure that corresponds to the exposed coupling surface.
| |
| − | * The innovation allows for the creation of an integrated circuit device with improved optical coupling capabilities.
| |
| | | | |
| − | '''Abstract'''
| |
| − | A method for manufacturing an integrated circuit device is provided. The method includes: providing a photonic structure including an insulating structure and an optical coupler embedded in the insulating structure; and removing a portion of the insulating structure to expose a coupling surface of the optical coupler and form a light reflective structure corresponding to the coupling surface.
| |
| | | | |
| − | ===CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE ([[US Patent Application 18360849. CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE simplified abstract|18360849]])=== | + | ===CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE ([[US Patent Application 18360849. CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18360849]])=== |
| | | | |
| | | | |
| Line 376: |
Line 228: |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME ([[US Patent Application 17829324. MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17829324]])=== |
| − | The patent application describes a method of operating a circuit that includes an operational amplifier, sampling switches, holding switches, and combined switches.
| |
| − | * The method involves four phases of operation.
| |
| − | * In the first phase, the sampling switches are closed, the holding switches are open, and the combined switches are open.
| |
| − | * In the second phase, the combined switches are closed.
| |
| − | * In the third phase, the sampling switches are open, the holding switches are closed, and the combined switches are open.
| |
| − | * In the fourth phase, the sampling switches are open, the holding switches are closed, and the combined switches are closed.
| |
| − | | |
| − | '''Abstract'''
| |
| − | A method of operating a circuit includes providing the circuit, the circuit includes an operational amplifier, a plurality of sampling switches, a plurality of holding switches, and a plurality of combined switches. The method further includes: during a first phase, causing the plurality of sampling switches to be closed, the plurality of the holding switches to be open, and the plurality of combined switches to be open; during a second phase, causing the plurality of combined switches to be closed; during a third phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be open; and during a fourth phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be closed.
| |
| − | | |
| − | ===MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME ([[US Patent Application 17829324. MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME simplified abstract|17829324]])=== | |
| | | | |
| | | | |
| Line 393: |
Line 234: |
| | | | |
| | MENG-HAN LIN | | MENG-HAN LIN |
| − |
| |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for forming an interconnect structure over a substrate, which includes a memory device with a transistor.
| |
| − |
| |
| − | * The method involves forming a first metallization layer and a second metallization layer over the first layer.
| |
| − | * A gate region of the transistor is formed in either the first or second metallization layer.
| |
| − | * A trench is etched in the second metallization layer to expose the gate region.
| |
| − | * A gate dielectric layer is deposited in the trench over the gate region.
| |
| − | * A channel layer is deposited in the trench over the gate dielectric layer.
| |
| − | * Two source/drain regions of the transistor are formed over the channel layer on opposite sides of the trench.
| |
| − | * The gate region and/or the channel layer may include two parallel first segments extending in the trench.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method includes: forming an interconnect structure over a substrate, the forming of the interconnect structure includes forming a memory device including a transistor. The forming of the interconnect structure includes: forming a first metallization layer and a second metallization layer over the first metallization layer; forming a gate region of the transistor in at least one of the first and second metallization layers; etching a trench disposed in the second metallization layer and exposing the gate region; depositing a gate dielectric layer in the trench over the gate region; depositing a channel layer in the trench over the gate dielectric layer; and forming two source/drain regions of the transistor over the channel layer on opposite sides of the trench. At least one of the gate region and the channel layer includes two first segments extending in the trench, wherein the first segments are parallel with each other.
| |
