Difference between revisions of "TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. patent applications published on November 30th, 2023"

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'''Summary of the patent applications from TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. on November 30th, 2023'''
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==Patent applications for TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. on November 30th, 2023==
 +
 
 +
===APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824930. APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824930]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
CHUN-HSI HUANG
 +
 
 +
 
 +
===METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18359900. METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18359900]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
YI-CHUAN TENG
  
−
Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has recently filed several patents related to various aspects of semiconductor device manufacturing and circuit operation. These patents cover methods for forming interconnect structures, operating circuits, manufacturing integrated circuit devices, fabricating semiconductor devices, and creating high-voltage devices. Notable applications include improved optical coupling capabilities, enhanced performance and functionality of high-voltage devices, improved dielectric properties for multilayer structures, and manufacturing methods for CMOS image sensors.
 
  
−
Summary:
+
===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME ([[US Patent Application 18359892. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18359892]])===
  
−
- TSMC has filed patents for methods of forming interconnect structures over substrates, including memory devices with transistors.
 
−
- They have also filed patents for methods of operating circuits, such as operational amplifiers, sampling switches, holding switches, and combined switches.
 
−
- TSMC's patents also cover methods for manufacturing integrated circuit devices using photonic structures and improved optical coupling capabilities.
 
−
- They have developed a semiconductor device with a metal gate layer, channel, and ferroelectric layer made of a hafnium oxide-based material with different phases.
 
−
- TSMC's patents also include methods for fabricating semiconductor devices, such as forming semiconductor fins, isolation regions, and recesses in substrates.
 
−
- They have developed a high-voltage device with specific structural features and doping configurations to enhance performance and functionality.
 
−
- TSMC's patents also cover multilayer structures with improved dielectric properties for use in electronic devices.
 
−
- They have developed semiconductor structures with capacitor structures and contact structures for improved electrical connections.
 
−
- TSMC's patents also include methods for manufacturing semiconductor structures for CMOS image sensors with improved performance and reliability.
 
−
- They have developed semiconductor structures with fins protruding from substrates and gate electrodes with conductive portions.
 
  
−
Notable Applications:
+
'''Main Inventor'''
  
−
* Improved optical coupling capabilities in integrated circuit devices.
+
CHING-KAI SHEN
−
* Enhanced performance and functionality of high-voltage devices.
 
−
* Improved dielectric properties for multilayer structures in electronic devices.
 
−
* Manufacturing methods for CMOS image sensors with improved performance and reliability.
 
  
  
 +
===ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION ([[US Patent Application 17827834. ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17827834]])===
  
  
−
==Patent applications for TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. on November 30th, 2023==
+
'''Main Inventor'''
 +
 
 +
CHIA-CHUN LIAO
 +
 
 +
 
 +
===VERTICAL POLARIZING BEAMSPLITTER FOR PHOTONICS ([[US Patent Application 17751777. VERTICAL POLARIZING BEAMSPLITTER FOR PHOTONICS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17751777]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
Tai-Chun Huang
 +
 
 +
 
 +
'''Brief explanation'''
 +
- The patent application describes a photonic polarizing beamsplitter.
 +
- The beamsplitter consists of a first waveguide and a second waveguide positioned above the first waveguide.
 +
- A birefringent coupler is present between the first and second waveguides.
 +
- The birefringent coupler has different effective refractive indices for TM and TE modes compared to the first waveguide.
 +
- The second waveguide is designed with outwardly tapering legs and a gap between adjacent legs, connected downstream to a body.
 +
- The innovation allows the vertical beamsplitter to occupy less surface area.
 +
 
 +
'''Abstract'''
 +
A photonic polarizing beamsplitter is disclosed. The beamsplitter comprises a first waveguide, a second waveguide located above the first waveguide, and a birefringent coupler between the first waveguide and the second waveguide. The birefringent coupler has an effective refractive index for a TM mode which is greater than a refractive index of the first waveguide, and an effective refractive index for a TE mode which is less than the refractive index of the first waveguide. The second waveguide comprises a plurality of outwardly tapering legs with a gap between adjacent legs that are connected downstream to a body. The vertical beamsplitter uses less surface area.
 +
 
 +
===VERTICAL GRATING COUPLER ([[US Patent Application 17751773. VERTICAL GRATING COUPLER simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17751773]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
Tai-Chun Huang
 +
 
 +
 
 +
'''Brief explanation'''
 +
The patent application describes a vertical grating coupler.
 +
* The grating coupler consists of a first waveguide, a second waveguide, and a dielectric layer between them.
 +
* The first waveguide has a first grating with ridges and gaps, and the second waveguide has a second grating with ridges and gaps.
 +
* The first grating, second grating, and dielectric layer are positioned in a vertical overlap region between the two waveguides.
 +
* The first and second gratings have different grating periods.
 +
* The gaps in both gratings are filled with the dielectric layer.
 +
 
 +
'''Abstract'''
 +
A vertical grating coupler is disclosed. The grating coupler includes a first waveguide having a first grating, a second waveguide having a second grating, and a dielectric layer positioned between the first waveguide and the second waveguide. The first grating includes a plurality of first grating ridges separated by a plurality first grating gaps, and the second grating includes a plurality of second grating ridges separated by a plurality second grating gaps. The first grating, the second grating, and the dielectric layer are located in a vertical overlap region between the first waveguide and the second waveguide. The first grating and the second grating have different grating periods, and each of the plurality of first grating gaps and second grating gaps are filled with the dielectric layer.
 +
 
 +
===VERTICAL GRATING FILTERS FOR PHOTONICS ([[US Patent Application 17751787. VERTICAL GRATING FILTERS FOR PHOTONICS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17751787]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
Tai-Chun Huang
 +
 
 +
 
 +
'''Brief explanation'''
 +
The abstract describes a photonic vertical grating filter that is used to improve filtering capabilities in a more compact design.
 +
 
 +
* The filter consists of a first waveguide, a second waveguide, and multiple Bragg gratings.
 +
* The Bragg gratings are located in a vertical overlap region between the first and second waveguides.
 +
* Each Bragg grating has a different grating period, allowing for different filtering capabilities.
 +
* The Bragg gratings are formed in a dielectric layer between the waveguides.
 +
* This vertical filter design requires less surface area compared to traditional filters.
 +
* The filter provides improved filtering capabilities due to the use of multiple Bragg gratings with different grating periods.
 +
 
 +
'''Abstract'''
 +
A photonic vertical grating filter is disclosed. The filter comprises a first waveguide, a second waveguide, and a plurality of Bragg gratings. The Bragg gratings are formed in a dielectric layer between the first waveguide and the second waveguide, and are located in a vertical overlap region between the first waveguide and the second waveguide. Each Bragg grating has a different grating period. The vertical filter uses less surface area and provides improved filtering capabilities.
 +
 
 +
===EUV PHOTOMASK AND MANUFACTURING METHOD OF THE SAME ([[US Patent Application 18361891. EUV PHOTOMASK AND MANUFACTURING METHOD OF THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18361891]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
FENG YUAN HSU
 +
 
 +
 
 +
===METHOD AND SYSTEM FOR SCANNING WAFER ([[US Patent Application 18359871. METHOD AND SYSTEM FOR SCANNING WAFER simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18359871]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
PEI-HSUAN LEE
 +
 
 +
 
 +
===WET PROCESSING SYSTEM AND SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824926. WET PROCESSING SYSTEM AND SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824926]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
YING-CHIEH MENG
 +
 
 +
 
 +
===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE ([[US Patent Application 17752976. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17752976]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
You-Ru Lin
 +
 
 +
 
 +
'''Brief explanation'''
 +
The patent application describes a semiconductor device and a method for creating such a device.
 +
* The device includes a MEMS component with one or more MEMS pixels, a MEMS membrane substrate, and a MEMS sidewall.
 +
* An analog circuit component is bonded to the MEMS component and includes at least one analog CMOS component within an analog circuit insulative layer and an analog circuit component substrate.
 +
* An HPC component is bonded to the analog circuit component substrate and includes at least one HPC metal component within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the bond pad and the HPC metal component, and an HPC substrate.
 +
* A DTC component is bonded to the HPC substrate and includes a DTC die within a DTC substrate.
 +
 
 +
'''Abstract'''
 +
A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.
 +
 
 +
===METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM ([[US Patent Application 17824942. METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824942]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
YUAN-CHENG YANG
 +
 
 +
 
 +
===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824936. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824936]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
JHU-MIN SONG
 +
 
 +
 
 +
===SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 18360855. SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18360855]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
WEI-LUN CHEN
 +
 
 +
 
 +
===SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824922. SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824922]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
CHING-HUNG KAO
 +
 
 +
 
 +
===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824924. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824924]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
JUI-LIN CHU
 +
 
 +
 
 +
===MULTILAYER STRUCTURE, CAPACITOR STRUCTURE AND ELECTRONIC DEVICE ([[US Patent Application 17827837. MULTILAYER STRUCTURE, CAPACITOR STRUCTURE AND ELECTRONIC DEVICE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17827837]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
HAI-DANG TRINH
 +
 
 +
 
 +
===HIGH VOLTAGE DEVICE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17827824. HIGH VOLTAGE DEVICE AND METHOD FOR FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17827824]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
YU-YING LAI
 +
 
 +
 
 +
===METHODS FOR DOPING SEMICONDUCTORS IN TRANSISTORS ([[US Patent Application 17826298. METHODS FOR DOPING SEMICONDUCTORS IN TRANSISTORS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17826298]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
Po-Hsun Ho
 +
 
 +
 
 +
'''Brief explanation'''
 +
The patent application describes methods for creating transistors using a single layer of semiconducting material with low contact resistance.
 +
* The source and drain terminals are positioned on opposite sides of the semiconducting layer from the gate terminal.
 +
* A dopant layer is applied to the contact and/or spacer regions of the semiconducting layer, covering them on the surface opposite the source and drain terminals.
 +
* The gate dielectric layer directly contacts the semiconducting layer.
 +
* This structure allows for high mobility in the semiconducting layer and reduces contact resistance.
 +
 
 +
'''Abstract'''
 +
Methods for making transistors with a semiconducting monolayer and low contact resistance are disclosed. The source/drain terminals are on opposite sides of the semiconducting monolayer from the gate terminal. The contact and/or spacer regions of the semiconducting monolayer are covered with a dopant layer on the surface opposite the source/drain terminals. The gate dielectric layer directly contacts the semiconducting monolayer. The resulting structure maintains high mobility in the semiconducting layer and has low contact resistance.
 +
 
 +
===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18232533. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18232533]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
Ya-Yi Tsai
 +
 
 +
 
 +
===HIGH-ELECTRON-MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING ([[US Patent Application 17752970. HIGH-ELECTRON-MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17752970]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
Pravanshu Mohanta
 +
 
 +
 
 +
'''Brief explanation'''
 +
- The patent application describes a method of manufacturing a High-Electron-Mobility Transistor (HEMT).
 +
- The method involves several steps, starting with preparing a substrate.
 +
- A first buffer is formed over the substrate, followed by a second buffer.
 +
- The second buffer is doped with a dopant such as carbon, with a gradient in concentration through its thickness.
 +
- A channel layer, such as GaN, is formed over the second buffer.
 +
- A barrier layer, such as aluminum gallium nitride (AlGaN), is formed over the channel layer.
 +
- Finally, drain, source, and gate terminals are formed for the HEMT.
 +
- The innovation lies in the specific doping technique used in the second buffer layer, which allows for a gradient in dopant concentration.
 +
- This gradient in dopant concentration may enhance the performance and efficiency of the HEMT.
 +
- The method described in the patent application provides a novel approach to manufacturing HEMTs, potentially leading to improved electronic devices.
 +
 
 +
'''Abstract'''
 +
A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.
 +
 
 +
===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTURE ([[US Patent Application 18360804. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18360804]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
CHUN-YEN PENG
 +
 
 +
 
 +
===METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT DEVICE THEREOF ([[US Patent Application 17824923. METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT DEVICE THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17824923]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
WEI-KANG LIU
 +
 
 +
 
 +
===HIGH-IMPLANT CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 18227236. HIGH-IMPLANT CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18227236]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
Chia-Chung CHEN
 +
 
 +
 
 +
'''Brief explanation'''
 +
The patent application describes a method for manufacturing a semiconductor device with an upper-channel implant transistor.
 +
* The method involves creating fins on a substrate, with a first region and second regions on either side.
 +
* A dopant is implanted in the upper portion of the first region of the fins, but not in the second regions or lower portion of the first region.
 +
* A gate structure is formed over the first region of the fins, extending in a perpendicular direction.
 +
* Source/drains are formed over the second regions of the fins.
 +
* This process results in the creation of an upper-channel implant transistor.
 +
 
 +
'''Abstract'''
 +
A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.
 +
 
 +
===CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE ([[US Patent Application 18360849. CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|18360849]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
BEI-SHING LIEN
 +
 
 +
 
 +
===MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME ([[US Patent Application 17829324. MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)|17829324]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 +
MENG-HAN LIN

Revision as of 08:50, 6 December 2023

Contents

Patent applications for TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. on November 30th, 2023

APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE (17824930)

Main Inventor

CHUN-HSI HUANG


METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE (18359900)

Main Inventor

YI-CHUAN TENG


SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME (18359892)

Main Inventor

CHING-KAI SHEN


ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION (17827834)

Main Inventor

CHIA-CHUN LIAO


VERTICAL POLARIZING BEAMSPLITTER FOR PHOTONICS (17751777)

Main Inventor

Tai-Chun Huang


Brief explanation 

- The patent application describes a photonic polarizing beamsplitter.

- The beamsplitter consists of a first waveguide and a second waveguide positioned above the first waveguide. - A birefringent coupler is present between the first and second waveguides. - The birefringent coupler has different effective refractive indices for TM and TE modes compared to the first waveguide. - The second waveguide is designed with outwardly tapering legs and a gap between adjacent legs, connected downstream to a body. - The innovation allows the vertical beamsplitter to occupy less surface area.

Abstract 

A photonic polarizing beamsplitter is disclosed. The beamsplitter comprises a first waveguide, a second waveguide located above the first waveguide, and a birefringent coupler between the first waveguide and the second waveguide. The birefringent coupler has an effective refractive index for a TM mode which is greater than a refractive index of the first waveguide, and an effective refractive index for a TE mode which is less than the refractive index of the first waveguide. The second waveguide comprises a plurality of outwardly tapering legs with a gap between adjacent legs that are connected downstream to a body. The vertical beamsplitter uses less surface area.

VERTICAL GRATING COUPLER (17751773)

Main Inventor

Tai-Chun Huang


Brief explanation 

The patent application describes a vertical grating coupler.
  • The grating coupler consists of a first waveguide, a second waveguide, and a dielectric layer between them.
  • The first waveguide has a first grating with ridges and gaps, and the second waveguide has a second grating with ridges and gaps.
  • The first grating, second grating, and dielectric layer are positioned in a vertical overlap region between the two waveguides.
  • The first and second gratings have different grating periods.
  • The gaps in both gratings are filled with the dielectric layer.

Abstract 

A vertical grating coupler is disclosed. The grating coupler includes a first waveguide having a first grating, a second waveguide having a second grating, and a dielectric layer positioned between the first waveguide and the second waveguide. The first grating includes a plurality of first grating ridges separated by a plurality first grating gaps, and the second grating includes a plurality of second grating ridges separated by a plurality second grating gaps. The first grating, the second grating, and the dielectric layer are located in a vertical overlap region between the first waveguide and the second waveguide. The first grating and the second grating have different grating periods, and each of the plurality of first grating gaps and second grating gaps are filled with the dielectric layer.

VERTICAL GRATING FILTERS FOR PHOTONICS (17751787)

Main Inventor

Tai-Chun Huang


Brief explanation 

The abstract describes a photonic vertical grating filter that is used to improve filtering capabilities in a more compact design.
  • The filter consists of a first waveguide, a second waveguide, and multiple Bragg gratings.
  • The Bragg gratings are located in a vertical overlap region between the first and second waveguides.
  • Each Bragg grating has a different grating period, allowing for different filtering capabilities.
  • The Bragg gratings are formed in a dielectric layer between the waveguides.
  • This vertical filter design requires less surface area compared to traditional filters.
  • The filter provides improved filtering capabilities due to the use of multiple Bragg gratings with different grating periods.

Abstract 

A photonic vertical grating filter is disclosed. The filter comprises a first waveguide, a second waveguide, and a plurality of Bragg gratings. The Bragg gratings are formed in a dielectric layer between the first waveguide and the second waveguide, and are located in a vertical overlap region between the first waveguide and the second waveguide. Each Bragg grating has a different grating period. The vertical filter uses less surface area and provides improved filtering capabilities.

EUV PHOTOMASK AND MANUFACTURING METHOD OF THE SAME (18361891)

Main Inventor

FENG YUAN HSU


METHOD AND SYSTEM FOR SCANNING WAFER (18359871)

Main Inventor

PEI-HSUAN LEE


WET PROCESSING SYSTEM AND SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE (17824926)

Main Inventor

YING-CHIEH MENG


SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (17752976)

Main Inventor

You-Ru Lin


Brief explanation 

The patent application describes a semiconductor device and a method for creating such a device.
  • The device includes a MEMS component with one or more MEMS pixels, a MEMS membrane substrate, and a MEMS sidewall.
  • An analog circuit component is bonded to the MEMS component and includes at least one analog CMOS component within an analog circuit insulative layer and an analog circuit component substrate.
  • An HPC component is bonded to the analog circuit component substrate and includes at least one HPC metal component within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the bond pad and the HPC metal component, and an HPC substrate.
  • A DTC component is bonded to the HPC substrate and includes a DTC die within a DTC substrate.

Abstract 

A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.

METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM (17824942)

Main Inventor

YUAN-CHENG YANG


SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17824936)

Main Inventor

JHU-MIN SONG


SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME (18360855)

Main Inventor

WEI-LUN CHEN


SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME (17824922)

Main Inventor

CHING-HUNG KAO


SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17824924)

Main Inventor

JUI-LIN CHU


MULTILAYER STRUCTURE, CAPACITOR STRUCTURE AND ELECTRONIC DEVICE (17827837)

Main Inventor

HAI-DANG TRINH


HIGH VOLTAGE DEVICE AND METHOD FOR FORMING THE SAME (17827824)

Main Inventor

YU-YING LAI


METHODS FOR DOPING SEMICONDUCTORS IN TRANSISTORS (17826298)

Main Inventor

Po-Hsun Ho


Brief explanation 

The patent application describes methods for creating transistors using a single layer of semiconducting material with low contact resistance.
  • The source and drain terminals are positioned on opposite sides of the semiconducting layer from the gate terminal.
  • A dopant layer is applied to the contact and/or spacer regions of the semiconducting layer, covering them on the surface opposite the source and drain terminals.
  • The gate dielectric layer directly contacts the semiconducting layer.
  • This structure allows for high mobility in the semiconducting layer and reduces contact resistance.

Abstract 

Methods for making transistors with a semiconducting monolayer and low contact resistance are disclosed. The source/drain terminals are on opposite sides of the semiconducting monolayer from the gate terminal. The contact and/or spacer regions of the semiconducting monolayer are covered with a dopant layer on the surface opposite the source/drain terminals. The gate dielectric layer directly contacts the semiconducting monolayer. The resulting structure maintains high mobility in the semiconducting layer and has low contact resistance.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18232533)

Main Inventor

Ya-Yi Tsai


HIGH-ELECTRON-MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING (17752970)

Main Inventor

Pravanshu Mohanta


Brief explanation 

- The patent application describes a method of manufacturing a High-Electron-Mobility Transistor (HEMT).

- The method involves several steps, starting with preparing a substrate. - A first buffer is formed over the substrate, followed by a second buffer. - The second buffer is doped with a dopant such as carbon, with a gradient in concentration through its thickness. - A channel layer, such as GaN, is formed over the second buffer. - A barrier layer, such as aluminum gallium nitride (AlGaN), is formed over the channel layer. - Finally, drain, source, and gate terminals are formed for the HEMT. - The innovation lies in the specific doping technique used in the second buffer layer, which allows for a gradient in dopant concentration. - This gradient in dopant concentration may enhance the performance and efficiency of the HEMT. - The method described in the patent application provides a novel approach to manufacturing HEMTs, potentially leading to improved electronic devices.

Abstract 

A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTURE (18360804)

Main Inventor

CHUN-YEN PENG


METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT DEVICE THEREOF (17824923)

Main Inventor

WEI-KANG LIU


HIGH-IMPLANT CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18227236)

Main Inventor

Chia-Chung CHEN


Brief explanation 

The patent application describes a method for manufacturing a semiconductor device with an upper-channel implant transistor.
  • The method involves creating fins on a substrate, with a first region and second regions on either side.
  • A dopant is implanted in the upper portion of the first region of the fins, but not in the second regions or lower portion of the first region.
  • A gate structure is formed over the first region of the fins, extending in a perpendicular direction.
  • Source/drains are formed over the second regions of the fins.
  • This process results in the creation of an upper-channel implant transistor.

Abstract 

A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE (18360849)

Main Inventor

BEI-SHING LIEN


MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME (17829324)

Main Inventor

MENG-HAN LIN

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