TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on April 4th, 2024
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on April 4th, 2024
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 56 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (21), H01L29/06 (17), H01L29/775 (16), H01L29/423 (15), H01L29/66545 (13)
With keywords such as: layer, structure, gate, semiconductor, substrate, dielectric, channel, device, forming, and between in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An SHIH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/027, H01L21/027
Abstract: a method of manufacturing a semiconductor device includes the following steps. a photoresist layer is formed over a material layer on a substrate. the photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. the first photo-active compound is represented by the following formula (a1) or formula (a2):
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An SHIH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/027, H01L21/027
Abstract:
zro(oh)(rco) formula (a1); or
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An SHIH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/027, H01L21/027
Abstract:
hfo(oh)(rco) formula (a2). r in the formula (a1) and r in the formula (a2) each include one of the following formulae (1) to (6):
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An SHIH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/027, H01L21/027
Abstract:
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-An SHIH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/027, H01L21/027
Abstract: the photoresist layer is patterned. the material layer is etched using the photoresist layer as an etch mask.
Inventor(s): Min-Shin Wu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Yu Chou of Chu Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05F3/26, H03F3/45
Abstract: in some aspects of the present disclosure, a bandgap reference circuit includes a first current mirror and a first resistor coupled to the first current mirror to provide a proportional to absolute temperature (ptat) voltage. the circuit includes a second current mirror and a bipolar junction transistor (bjt) device coupled to the second current mirror to provide a complementary to the absolute temperature (ctat) voltage. the circuit includes an output node to provide a bandgap voltage that is a weighted sum of the ptat voltage and the ctat voltage. the circuit includes a second resistor coupled between the output node and a first node, wherein the first node is coupled between the first resistor and the first current mirror. the circuit includes a third resistor coupled between the output node and a second node, wherein the second node is coupled between the bjt device and the second current mirror.
Inventor(s): Ke-Ying SU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Wei SU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Hua KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lester CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/20
Abstract: a method of generating an ic layout diagram includes receiving the ic layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.
Inventor(s): Shigeki SHIMOMURA of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd., Yongxi LI of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4091, G11C11/4074, G11C11/4076
Abstract: a memory device includes a memory array and a sense amplifier. the sense amplifier operates with a first supply voltage and be enabled, in response to an enable signal, to receive first and second current signals from the memory array through first and second nodes, and includes a pull-up circuit and a latch circuit. the pull-up circuit is coupled between a first supply voltage terminal and the first to second nodes, and couples, in response to a first control signal having a low logic state, the first supply voltage terminal to the first and second nodes. the latch circuit generates, in response to the first and second current signals received from the first and second nodes, first and second output signals for determining a data stored in a memory cell in the memory array when the first supply voltage terminal is coupled to the first and second nodes.
Inventor(s): Po-Sheng Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hung Liu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Nuo Xu of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01F17/02
Abstract: an inductor and a method of forming the same are provided. the inductor includes a patterned wire structure. the patterned wire structure includes a conductive core, a dielectric film and a magnetic shell. the conductive core includes a pair of end surfaces and an outer surface between the pair of end surfaces. the dielectric film covers the outer surface. the magnetic shell covers the dielectric film. the dielectric film is between the conductive core and the magnetic shell.
Inventor(s): Ching-Yu Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jei Ming Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/3065, H01L21/308, H01L21/768
Abstract: a method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. a gap-filling material is deposited in the opening. a plasma treatment is performed on the gap-filling material. the height of the gap-filling material is reduced. the mask layer is removed. the substrate is patterned using the gap-filling material as a mask.
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, G03F7/004, G03F7/20, H01L21/311
Abstract: a method of manufacturing a semiconductor device includes the following steps. a photoresist layer is formed over a material layer on a substrate. the photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. the first photo-active compound is represented by the following formula (al) or formula (a2):
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, G03F7/004, G03F7/20, H01L21/311
Abstract:
zro(oh)(rco) formula (a);
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, G03F7/004, G03F7/20, H01L21/311
Abstract: or
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, G03F7/004, G03F7/20, H01L21/311
Abstract:
hfo(oh)(rco) formula (a).
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, G03F7/004, G03F7/20, H01L21/311
Abstract: r in the formula (a1) and r in the formula (a2) each include one of the following formulae (1) to (6):
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, G03F7/004, G03F7/20, H01L21/311
Abstract:
Inventor(s): Jui-Hsiung LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fang TSENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chia LIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng GAU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiung CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wen CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, G03F7/004, G03F7/20, H01L21/311
Abstract: the photoresist layer is patterned. the material layer is etched using the photoresist layer as an etch mask.
Inventor(s): Hsu-Hsien Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yen Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chih Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/56, H01L21/306, H01L21/768, H01L21/78, H01L23/522, H01L23/538
Abstract: an integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. the integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. the first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. the first angle may be larger than the second angle.
20240112928.TRIMMING METHOD_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): An-Hsuan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hao Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hung Liao of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/02, H01L21/304
Abstract: a trimming method is provided. the trimming method includes the following steps. a first wafer including a substrate and a device layer over a first side of the substrate is provided. the first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. an edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction. a grinding process is performed on the untrimmed portion of the substrate from the second side to thin the untrimmed portion of the substrate to a reduced thickness in the first direction, wherein the grinding process results in the reduced thickness being greater than a thickness of the flange pattern.
Inventor(s): Ming-Hsun LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/8234
Abstract: some implementations described herein include an integrated circuit device including landing circuitry and methods of formation. the landing circuitry, which may be part of a trench capacitor region, includes a stair-shaped profile that extends into a silicon substrate of the integrated circuit device. the landing circuitry includes electrode layers of the trench capacitor region interspersed with layers of a dielectric material. the landing circuitry further includes spacer structures on ends of the electrode layers along the stair-shaped profile.
Inventor(s): Yu-Xuan Wang of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chun Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsien Lin of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092
Abstract: a fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.
Inventor(s): Sai-Hooi YEONG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Hsuan LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/768, H01L27/092, H01L29/08, H01L29/66, H01L29/78
Abstract: a method of forming a device includes providing a transistor having a gate structure and a source/drain structure adjacent to the gate structure. a cavity is formed along a sidewall surface of a contact opening over the source/drain structure. after forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. a first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source/drain structure. a metal plug is then formed over the portion of the exposed source/drain structure. a remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. thereafter, a seal layer is deposited over the air gap to form an air gap spacer.
Inventor(s): Kuan-Ting PAN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Zhi-Chang LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ruei JHAN of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/311, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/786
Abstract: a method of fabricating a device includes forming a dummy gate over a plurality of fins. thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. the method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. the method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
Inventor(s): Li WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chang KU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/46, H01L21/52, H01L21/56, H01L23/00, H01L23/31, H10B80/00
Abstract: a semiconductor device includes a substrate, a semiconductor component and a heat dissipation component. the semiconductor component is disposed on the substrate. the heat dissipation component is disposed on the substrate and having a cavity, an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity.
Inventor(s): Fu-Ting SUNG of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L23/528, H10B63/00, H10N70/00
Abstract: a cell structure of a memory device includes an upper electrode structure separated from a metal line above the cell structure by a combination of one or more layers including an isolation layer. the cell structure may be patterned using a metal line below the cell structure as an etch-stop layer. relative to other techniques that include patterning the cell structure using a silicon carbide layer located over the metal line below the cell structure as an etch-stop layer, the techniques described herein may reduce an overall height of the memory structure. additionally, or alternatively, the techniques may maintain or increase an isolation distance between the metal line above the cell structure and the upper electrode structure. in this way, a likelihood of shorting between the metal line above the cell structure and the upper electrode structure is reduced to improve a performance and/or a reliability of the memory device.
Inventor(s): Wen-Chiung Tu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chiu Huang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
Abstract: semiconductor structures and methods are provided. an exemplary method includes forming a first conductive feature in a dielectric layer, forming a metal-insulator-metal (mim) capacitor over the dielectric layer, forming a first passivation structure over the mim capacitor, forming a first contact via opening extending through the first passivation structure and the mim capacitor to expose the first conductive feature, depositing a conductive material to fill the first contact via opening, performing a first etching process to the conductive material to form a first metal feature, the first metal feature comprising a first portion filling the first contact via opening and a second portion over the first passivation structure, and performing a second etching process to trim the second portion of the first metal feature, after the second etching process, a shape of a cross-sectional view of the second portion of the first metal feature comprises a barrel shape.
Inventor(s): Kai-Fung CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Wei LIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Feng WENG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Yu YEN of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Cheyu LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chih CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Yang LEI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L25/10
Abstract: interconnect structure packages (e.g., through silicon vias (tsv) packages, through interlayer via (tiv) packages) may be pre-manufactured as opposed to forming tivs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. the interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. a molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
Inventor(s): Yu-Hung LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ming WANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao YU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., PaoTai HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Hsuan LO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng TAI of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/544, H01L21/768, H01L23/00, H01L23/48, H01L25/00
Abstract: a method for forming a semiconductor package is provided. the method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. the method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. the method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.
Inventor(s): Hsing-Kuo Hsia of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui Lin Chao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, G02B6/12, G02B6/13, H01L23/498, H10B80/00
Abstract: a semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.
Inventor(s): Ching-Wen Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Sen Chang of Jinsha Township (TW) for taiwan semiconductor manufacturing company, ltd., Shou-Cheng Hu of Tai-Chung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/48, H01L23/522, H01L23/528, H01L23/538, H01L23/64
Abstract: a semiconductor device and a method of manufacture are provided. in particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. embodiments such as those disclosed herein may be utilized in pop applications. in an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. one or more dies and/or packages may be attached to the interconnection layers.
Inventor(s): Tian Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Han Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sih-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L21/56, H01L23/00, H01L23/31, H01L25/00
Abstract: a semiconductor package and a manufacturing method thereof are provided. the semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. the die has a front surface and a back surface opposite to the front surface. the underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. the patterned dielectric layer is disposed on the back surface of the die. the conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.
Inventor(s): Fang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/8238, H01L27/092, H01L27/118, H01L29/06
Abstract: an integrated circuit includes a first standard cell having a first pfet and a first nfet integrated, and having a first dielectric gate on a first standard cell boundary. the integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pfet and a second nfet integrated, and having a second dielectric gate on a second standard cell boundary. the integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. the first pfet and the second pfet are formed on a first continuous active region. the first nfet and the second nfet are formed on a second continuous active region.
Inventor(s): Chia-Lin HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ti SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L27/06, H01L27/092, H01L29/08
Abstract: an ic device includes first and second cmos structures positioned in n-type doped regions of a substrate, the first cmos structure including a common gate terminal, first nmos body and source contacts, and first pmos body and source contacts, the second cmos structure including a common drain terminal, second nmos body and source contacts, and second pmos body and source contacts. the ic device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first pmos body and source contacts, and a third electrical connection from an anode of the of the diode to the first nmos body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the ic device.
Inventor(s): Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chung Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Hua Hsu of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsien Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ching Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Wei Yin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Wen Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/3065, H01L21/3213, H01L21/762, H01L21/8234, H01L27/02, H01L29/06, H01L29/66, H01L29/78
Abstract: methods of cutting gate structures and fins, and structures formed thereby, are described. in an embodiment, a substrate includes first and second fins and an isolation region. the first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. a gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. a first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. no portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. a second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. the first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
Inventor(s): Chih-Chang Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ching Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Yuan Ku of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsuan Hsiao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., I-Wei Yang of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/283, H01L21/311, H01L21/3213, H01L21/762, H01L21/8234, H01L29/06, H01L29/08, H01L29/423, H01L29/49, H01L29/66, H01L29/78
Abstract: methods of cutting gate structures, and structures formed, are described. in an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. the first and second gate structures extend parallel. the active area includes a source/drain region disposed laterally between the first and second gate structures. the gate cut-fill structure has first and second primary portions and an intermediate portion. the first and second primary portions abut the first and second gate structures, respectively. the intermediate portion extends laterally between the first and second primary portions. first and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
Inventor(s): Tetsu Ohtou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Jia Huang of Beigang Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsing Hsu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/786
Abstract: the present disclosure describes a method for the formation of gate-all-around nano-sheet fets with tunable performance. the method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. the method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.
Inventor(s): Ming-Heng TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L29/06, H01L29/423, H01L29/775
Abstract: semiconductor devices are provided. a semiconductor device includes a first well region having a first conductivity type, a second well region having a second conductivity type, a cell, and a pickup tap cell. the cell includes a first forksheet structure. the first forksheet structure includes a first transistor formed over the first well region, a second transistor formed over the second well region, and a first wall structure disposed on and extending along an interface between the first and second well regions. the first transistor and the second transistor are disposed on opposite sides of the first wall structure. the pickup tap cell includes a nanosheet structure. the nanosheet structure includes a pickup transistor formed over the second well region. source/drain features of the first transistor and the pickup transistor have the second conductivity type, and source/drain features of the second transistor have the first conductivity type.
Inventor(s): Cheng Yu Huang of Hsinchu (CN) for taiwan semiconductor manufacturing company, ltd., Wen-Hau Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Yu Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chieh Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Kung Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, G02B3/00
Abstract: various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. the first image sensor element is adjacent to the second image sensor element. a first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. a second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.
Inventor(s): Shu-Hui SU of Tucheng City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Li CHENG of Hsin Chu (TW) for taiwan semiconductor manufacturing company, ltd., YingKit Felix TSUI of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/522, H01L23/60
Abstract: a semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. at least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. the depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.
Inventor(s): Heng-Chia Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Fong Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zhen-Cheng Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/762, H01L21/768, H01L21/8234, H01L29/66, H01L29/78, H01L29/786
Abstract: a process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. after forming the edge area, another dielectric fill material is provided in the edge area. in the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng Liang of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Chang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
Abstract: a semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. the substrate includes a first fin and a second fin. the first stack of semiconductor nanosheets is disposed on the first fin. the second stack of semiconductor nanosheets is disposed on the second fin. the gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. the first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. the first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.
Inventor(s): Tzu-Ging Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Liang Lai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chen Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Yuan Ku of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shun-Hui Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/786
Abstract: a method for fabricating semiconductor devices includes forming channel regions over a substrate. the channel regions, in parallel with one another, extend along a first lateral direction. each channel region includes at least a respective pair of epitaxial structures. the method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. the method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. the method includes removing, through a second etching process, a portion of the first channel region. the second etching process includes one silicon etching process and one silicon oxide deposition process. the method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.
Inventor(s): Yi-Tse Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Zhan Li of () for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Iuliana Radu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/8234, H01L29/10, H01L29/18, H01L29/66, H01L29/78
Abstract: a semiconductor device includes a substrate, a channel layer, a gate structure, source/drain regions, and an insulating layer. the channel layer is disposed over the substrate. the gate structure is disposed over the channel layer. the source/drain regions are disposed over the substrate and disposed at two opposite sides of the channel layer. the insulating layer is disposed between the channel layer and the source/drain regions.
Inventor(s): Wei Ju Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu Cheng of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei Wu of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/02, H01L29/423, H01L29/45, H01L29/786
Abstract: in one example aspect, the present disclosure is directed to a device. the device includes an active region on a semiconductor substrate. the active region extends along a first direction. the device also includes a gate structure on the active region. the gate structure extends along a second direction that is perpendicular to the first direction. moreover, the gate structure engages with a channel on the active region. the device further includes a source/drain feature on the active region and connected to the channel. a projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L29/66, H01L29/78
Abstract: methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. in an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (alw); and a fill material over the first work function tuning layer.
Inventor(s): Jhu-Min Song of Nantou City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Chou Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Kai Ciou of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chih Chou of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Fei-Yun Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chang Jong of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Te Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088
Abstract: the present disclosure relates to an integrated chip. the integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. source/drain regions are disposed within the substrate on opposing sides of the recess. a first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. a gate electrode is disposed on the second gate dielectric. the second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.
Inventor(s): Wen-Li CHIU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Juei LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jie YE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsin CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Jun LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/775
Abstract: an integrated circuit (ic) structure includes a semiconductor substrate, a first gate line, a second gate line, and a first auxiliary gate portion. the semiconductor substrate comprises a semiconductor fin. the semiconductor fin extends substantially along a first direction. the first gate line and the second gate line extend substantially along a second direction different form the first direction from a top view. the first auxiliary gate portion connects the first gate line to the second gate line from the top view.
Inventor(s): Jia-Ni YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kun CHU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei HSU of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Lin HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/66, H01L29/775, H01L29/786
Abstract: semiconductor structures and methods for forming the same are provided. the semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. the semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. the semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.
Inventor(s): Ko-Cheng LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Miao LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/225, H01L21/265, H01L21/266, H01L29/06, H01L29/10, H01L29/423, H01L29/775
Abstract: a method of fabricating a device includes providing a plurality of fins extending from a substrate. in some embodiments, each fin of the plurality of fins includes a plurality of semiconductor channel layers. in various example, the method further includes performing an ion implantation process into a first fin of the plurality of fins to introduce a dopant species into a topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin. in some embodiments, the ion implantation process deactivates the topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin.
Inventor(s): Jia-Chuan YOU of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/417, H01L29/423, H01L29/775
Abstract: a method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. an interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. the insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.
Inventor(s): Chih-Ching WANG of Kinmen County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Yu LAI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-I YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-En LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775
Abstract: methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. in some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. in some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially v-shaped recesses. in some embodiments, the method further includes forming a substantially v-shaped inner spacer within the substantially v-shaped recesses.
Inventor(s): Wen-Kai Lin of Yilan (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Yu Lai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li Chun Te of Renwu Township (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Hsuan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-I Bao of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ken Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/08, H01L29/78
Abstract: embodiments of the present disclosure relate to a finfet device having gate spacers with reduced capacitance and methods for forming the finfet device. particularly, the finfet device according to the present disclosure includes gate spacers formed by two or more depositions. the gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
Inventor(s): Che-Lun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/08, H01L29/423, H01L29/786
Abstract: a method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. a first spacer layer is deposited over the gate and over the fin in a source/drain region. the first spacer layer has a first etch rate. a second spacer layer is deposited over the first spacer layer. the second spacer layer has a second etch rate less than the first etch rate. the plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. after forming the trench, inner spacers are formed along a sidewall surface of the trench. in various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.
Inventor(s): Chih-Chiang Chang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Li Su of Chubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/20, H01L21/8234, H01L27/092, H01L29/417, H01L29/78
Abstract: a method includes forming a first semiconductor fin and a second semiconductor fin in an n-type fin field-effect (finfet) region and a p-type finfet region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type finfet region and the p-type finfet region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. after the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.
Inventor(s): Yu-Lien HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/78
Abstract: a method includes forming a first multilayer interconnection structure over a carrier substrate. a first interlayer dielectric (ild) layer is deposited over the first multilayer interconnection structure. a first source/drain contact is formed in the first ild layer. after forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ild layer. the semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. a gate structure is formed across the semiconductor fin. the semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. first and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.
Inventor(s): Che-Lun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting Pan of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/417, H01L29/423, H01L29/66
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes a first channel member suspended over a substrate and a second channel member suspended over the first channel member and spaced apart from the first channel member along a first direction. the semiconductor structure also includes a gate structure wrapping around the first channel member and the second channel member and a dielectric structure encircled by the first channel member, the second channel member, the gate structure, and the source/drain structure. in addition, the dielectric structure includes a porous material or an air gap. the semiconductor structure also includes a first epitaxial layer attached to the first channel member, and the first epitaxial layer has a first extending portion protruding from a bottom surface of the first channel member along the first direction and extending into the dielectric structure.
Inventor(s): Chun-Hsiung TSAI of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yi PENG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Feng YU of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Ziwei FANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/265, H01L21/3065, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/165, H01L29/167, H01L29/45, H01L29/66
Abstract: a fin field effect transistor (finfet) device structure is provided. the finfet device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. the finfet device structure includes a source/drain (s/d) structure over the fin structure, and the s/d structure is adjacent to the gate structure. the finfet device structure also includes a metal silicide layer over the s/d structure, and the metal silicide layer is in contact with the isolation structure.
Inventor(s): Yan-Yi Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wu-Wei Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Hsiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L27/07, H01L29/66
Abstract: some embodiments relate to a thin film transistor comprising an active layer over a substrate. an insulator is stacked with the active layer. a gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. the first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.
Inventor(s): Wu-Wei Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Yi Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/08, H01L29/66
Abstract: a semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. the gate insulating layer is located between the gate and the semiconductor structure. the semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. the first oxide layer is located between the first metal oxide layer and the second metal oxide layer. the first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.
Inventor(s): Ya-Yun Cheng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ling Lu of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chien Chiu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei Wu of Ju-Bei City (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/66
Abstract: an integrated chip including a gate layer. an insulator layer is over the gate layer. a channel structure is over the insulator layer. a pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. the channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. the first channel layer, the second channel layer, and the third channel layer include different semiconductors.
Inventor(s): TsuChing Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chang Sun of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo Chang Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L29/06, H10B51/10
Abstract: a method of forming a three-dimensional (3d) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (sls) and bit lines (bls) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the sls and bls.
Inventor(s): Chih-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/30, G11C11/22
Abstract: a semiconductor device includes a ferroelectric field-effect transistor (fefet), wherein the fefet includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. the gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.
Inventor(s): Tzu-Yu CHEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hung SHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Chen CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chi TU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ting CHU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Alexander KALNITSKY of San Francisco CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30
Abstract: a semiconductor device includes a substrate, a bottom electrode, a ferroelectric layer, a noble metal electrode, and a non-noble metal electrode. the bottom electrode is over the substrate. the ferroelectric layer is over the bottom electrode. the noble metal electrode is over the ferroelectric layer. the non-noble metal electrode is over the noble metal electrode.
Inventor(s): Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng Tai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B80/00, H10B61/00, H10N50/01, H10N50/20, H10N50/80
Abstract: a semiconductor device includes a first substrate, a transistor, an interconnection structure, a first bonding pad, a magnetic tunnel junction (mtj) structure, a conductive line and a second substrate. the transistor is formed on the first substrate. the interconnection structure is formed on the first substrate and electrically connected to the transistor. the first bonding pad is formed on and electrically connected to the interconnection structure. the mtj structure is disposed on and electrically connected to the first bonding pad, wherein the mtj structure comprises a free layer, a tunnel barrier layer, a synthetic antiferromagnet layer sequentially stacked up over the first bonding pad. the conductive line is disposed on the mtj structure. the second substrate is disposed on the conductive line.
Inventor(s): Tsung-Fu TSAI of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng TAI of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B80/00, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/48
Abstract: a package structure and a formation method are provided. the method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. the method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. the method further includes forming a protective layer surrounding the second chip structure. a portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on April 4th, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- G03F7/004
- G03F7/027
- H01L21/027
- Taiwan semiconductor manufacturing company, ltd.
- G05F3/26
- H03F3/45
- G06F30/392
- G06F30/20
- G11C11/4091
- G11C11/4074
- G11C11/4076
- H01F17/02
- H01L21/02
- H01L21/3065
- H01L21/308
- H01L21/768
- G03F7/20
- H01L21/311
- H01L21/56
- H01L21/306
- H01L21/78
- H01L23/522
- H01L23/538
- H01L21/67
- H01L21/304
- H01L21/8234
- H01L21/8238
- H01L27/092
- H01L29/08
- H01L29/66
- H01L29/78
- H01L29/06
- H01L29/417
- H01L29/423
- H01L29/786
- H01L23/46
- H01L21/52
- H01L23/00
- H01L23/31
- H10B80/00
- H01L23/48
- H01L23/528
- H10B63/00
- H10N70/00
- H01L21/48
- H01L23/498
- H01L25/10
- H01L23/544
- H01L25/00
- G02B6/12
- G02B6/13
- H01L25/065
- H01L21/683
- H01L23/64
- H01L27/02
- H01L27/118
- H01L27/06
- H01L27/088
- H01L21/3213
- H01L21/762
- H01L21/283
- H01L29/49
- H01L29/775
- H01L27/146
- G02B3/00
- H01L23/60
- H01L29/10
- H01L29/18
- H01L29/45
- H01L21/225
- H01L21/265
- H01L21/266
- H01L21/20
- H01L29/165
- H01L29/167
- H01L27/07
- H10B51/20
- H10B51/10
- H10B51/30
- G11C11/22
- H10B53/30
- H10B61/00
- H10N50/01
- H10N50/20
- H10N50/80
- H01L29/66545
