Sk hynix inc. (20240120020). MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE simplified abstract
Contents
- 1 MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE
Organization Name
Inventor(s)
Byung Wook Bae of Icheon-si Gyeonggi-do (KR)
Jung Ryul Ahn of Icheon-si Gyeonggi-do (KR)
MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240120020 titled 'MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE
Simplified Explanation
The abstract describes a memory device with a first chip containing a memory cell array and a second chip overlapping with the first chip. The second chip includes a semiconductor substrate with a peripheral circuit area and a lower test area, sub-test pads, sub-test circuits, and a detection circuit.
- Memory device with two chips overlapping each other
- Second chip includes sub-test pads, sub-test circuits, and a detection circuit
- Detection circuit outputs a signal based on input signals from sub-test circuits
Potential Applications
This technology can be applied in the semiconductor industry for testing memory devices efficiently and accurately.
Problems Solved
This technology helps in detecting failures in memory devices during testing, ensuring high quality and reliability.
Benefits
The memory device with the described structure allows for thorough testing of memory cells, leading to improved overall performance and longevity.
Potential Commercial Applications
The technology can be utilized in the production of memory devices for various electronic devices, ensuring their reliability and quality.
Possible Prior Art
One possible prior art could be the use of separate testing equipment for memory devices, which may not be as efficient or cost-effective as the integrated testing method described in this patent application.
Unanswered Questions
How does this technology compare to traditional memory testing methods?
This article does not provide a direct comparison between this technology and traditional memory testing methods.
What are the specific signals that the detection circuit analyzes to determine memory device failure?
The article does not delve into the specific signals that the detection circuit analyzes for determining memory device failure.
Original Abstract Submitted
a memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. the second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.
