Samsung electronics co., ltd. (20240136331). SEMICONDUCTOR PACKAGE simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Hyun Soo Chung of Suwon-si (KR)
Young Lyong Kim of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240136331 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a circuit board, an interposer structure, a mold layer, and two semiconductor chips connected to the interposer structure. The mold layer wraps around the chips and includes a penetrating portion in a plurality of trenches on the interposer structure.
- The semiconductor package includes a circuit board, interposer structure, mold layer, and two semiconductor chips.
- The interposer structure has a center region where the chips are spaced apart in a first direction and electrically connected.
- The mold layer wraps around the chips and includes a penetrating portion in trenches on the interposer structure.
- The bottom surface of the penetrating portion of the mold layer is on the same plane as the bottom surface of the interposer structure.
Potential Applications
This technology could be used in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics where compact and efficient semiconductor packaging is required.
Problems Solved
This innovation solves the problem of efficiently packaging and connecting multiple semiconductor chips in a compact and reliable manner, reducing the overall size of electronic devices while maintaining performance.
Benefits
The benefits of this technology include improved thermal performance, reduced footprint, increased reliability, and enhanced electrical connectivity between semiconductor chips.
Potential Commercial Applications
One potential commercial application of this technology could be in the development of advanced mobile devices with increased processing power and reduced size, catering to the demands of the modern consumer electronics market.
Possible Prior Art
One possible prior art for this technology could be the use of stacked semiconductor chips in electronic devices, but the specific arrangement and structure described in this patent application may be novel and inventive.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods?
This article does not provide a direct comparison to existing semiconductor packaging methods, leaving the reader to wonder about the specific advantages and disadvantages of this innovation in relation to current practices.
What are the potential challenges in implementing this technology on a large scale?
The article does not address the potential challenges in scaling up the production of semiconductor packages using this technology, leaving room for speculation on the feasibility and cost-effectiveness of mass production.
Original Abstract Submitted
a semiconductor package may include a circuit board, an interposer structure on the circuit board, a mold layer, and a first semiconductor chip and a second semiconductor chip spaced apart from each other in a first direction on a center region of the interposer structure and electrically connected to the interposer structure. the interposer structure may include a plurality of trenches in an edge region of the interposer structure and extending through the interposer structure. the mold layer may be in the plurality of trenches and may wrap the first and second semiconductor chips. the mold layer may include a penetrating portion in the plurality of trenches and a stack portion on the interposer structure. a bottom surface of the penetrating portion of the mold layer may be on a same plane as a bottom surface of the interposer structure.
