Samsung electronics co., ltd. (20240136201). SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract

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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Organization Name

samsung electronics co., ltd.

Inventor(s)

Yuseon Heo of Suwon-si (KR)

Junhyeong Park of Suwon-si (KR)

Jieun Park of Suwon-si (KR)

Jihye Shim of Suwon-si (KR)

Jiyoung Lee of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240136201 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The method described in the patent application involves manufacturing a semiconductor package by forming wiring structures, coating high transmittance photoresist, creating openings, filling them with conductive material, placing a semiconductor chip, encapsulating it, and forming additional wiring structures.

  • Formation of wiring structures
  • Coating with high transmittance photoresist multiple times
  • Creating openings through exposure and development
  • Filling openings with conductive material to create posts
  • Removing photoresist
  • Placing semiconductor chip and encapsulating it
  • Forming additional wiring structures

Potential Applications

The technology can be applied in the manufacturing of various semiconductor devices, such as integrated circuits, sensors, and microprocessors.

Problems Solved

This method helps in improving the efficiency and reliability of semiconductor packaging by enhancing light transmittance and ensuring proper electrical connections within the package.

Benefits

- Enhanced light transmittance - Improved electrical connections - Increased reliability of semiconductor packages

Potential Commercial Applications

The technology can be utilized in the production of consumer electronics, automotive electronics, medical devices, and industrial equipment.

Possible Prior Art

Prior art may include similar methods of manufacturing semiconductor packages using photoresist coatings and conductive materials, but with potentially lower light transmittance properties.

Unanswered Questions

How does this method compare to traditional semiconductor packaging techniques?

This article does not provide a direct comparison between this innovative method and traditional semiconductor packaging techniques. It would be beneficial to understand the specific advantages and disadvantages of this new approach in comparison to existing methods.

What are the specific characteristics of the conductive material used in filling the openings?

The article does not delve into the details of the conductive material utilized in the process. Understanding the properties and composition of this material could provide insights into the overall performance and reliability of the semiconductor package.


Original Abstract Submitted

provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, coating a high transmittance photoresist on the first wiring structure a plurality of number of times, forming a plurality of openings by exposing and developing the high transmittance photoresist, forming a plurality of conductive posts by filling the plurality of openings with a conductive material, removing the high transmittance photoresist, disposing a semiconductor chip on the first wiring structure, forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the light transmittance of the high transmittance photoresist at a portion where the first wiring structure and the high transmittance photoresist contact each other is greater than or equal to 3.2%.