Samsung electronics co., ltd. (20240128225). SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract

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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Organization Name

samsung electronics co., ltd.

Inventor(s)

Hajung Lee of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240128225 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The semiconductor package described in the patent application includes a first semiconductor chip, multiple second semiconductor chips stacked on top of the first chip, connection pads on the lower and upper surfaces of the chips, a chip connection terminal, and an insulating adhesive layer with two material layers of different viscosities.

  • The semiconductor package consists of multiple stacked semiconductor chips.
  • Connection pads are located on the lower and upper surfaces of the chips for connectivity.
  • An insulating adhesive layer with two material layers is used to secure the chips together.

Potential Applications

The technology described in this patent application could be applied in:

  • High-density memory modules
  • Advanced microprocessors
  • Power management systems

Problems Solved

This technology addresses issues such as:

  • Improving thermal management in stacked semiconductor packages
  • Enhancing electrical connectivity between chips
  • Increasing overall reliability of semiconductor devices

Benefits

The benefits of this technology include:

  • Higher performance in compact electronic devices
  • Improved signal transmission between semiconductor chips
  • Enhanced durability and longevity of semiconductor packages

Potential Commercial Applications

This technology could be utilized in various industries, including:

  • Consumer electronics
  • Automotive electronics
  • Telecommunications equipment

Possible Prior Art

One possible prior art for this technology could be the use of insulating adhesive layers in semiconductor packaging to improve connectivity and reliability.

Unanswered Questions

How does this technology impact the overall cost of semiconductor packaging?

The cost implications of implementing this technology in semiconductor packaging are not addressed in the patent application.

What are the environmental implications of using insulating adhesive layers in semiconductor packaging?

The environmental impact of the materials used in the insulating adhesive layers is not discussed in the patent application.


Original Abstract Submitted

a semiconductor package is provided. the semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a front connection pad disposed on a lower surface of the plurality of second semiconductor chips, a rear connection pad attached on an upper surface of the first semiconductor chip and the second semiconductor chips, a chip connection terminal disposed between the front connection pad and the rear connection pad, and an insulating adhesive layer disposed between the first semiconductor chip and a lowermost second semiconductor chip and between two adjacent second semiconductor chips, the insulating adhesive layer including a first material layer covering a sidewall of the chip connection terminal and having first viscosity and a second material layer disposed to surround the first material layer in a plan view and have second viscosity which is greater than the first viscosity.