Samsung electronics co., ltd. (20240096773). SEMICONDUCTOR PACKAGE simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Kyounglim Suk of Suwon-si (KR)
Hyeonjeong Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240096773 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a redistribution structure with alternating redistribution and insulating layers, a semiconductor chip connected to the redistribution layer, and bumps on the structure. The redistribution structure features vias and under bump metallurgy (UBM) structures for electrical connections between the vias and bumps.
- The semiconductor package includes a redistribution structure with vias and UBM structures.
- The UBM structures consist of a first UBM layer with a metal material and a second UBM layer with a different metal material.
Potential Applications
This technology could be applied in various semiconductor devices, such as integrated circuits, microprocessors, and memory chips.
Problems Solved
This technology helps improve the electrical connections within semiconductor packages, leading to enhanced performance and reliability of electronic devices.
Benefits
The use of vias and UBM structures in the redistribution structure improves the electrical connectivity and signal transmission efficiency in semiconductor packages.
Potential Commercial Applications
"Enhancing Electrical Connectivity in Semiconductor Packages: Applications and Benefits"
Possible Prior Art
There may be prior art related to the use of vias and UBM structures in semiconductor packaging for improved electrical connections.
Unanswered Questions
How does this technology impact the overall size and weight of semiconductor packages?
The abstract does not provide information on the potential effects of this technology on the size and weight of semiconductor packages.
Are there any specific manufacturing processes required for implementing this technology?
The abstract does not mention any specific manufacturing processes needed for the implementation of this technology.
Original Abstract Submitted
a semiconductor package includes a redistribution structure in which at least one redistribution layer and at least one insulating layer are alternately stacked; a semiconductor chip electrically connected to the at least one redistribution layer; and bumps on the redistribution structure, wherein the redistribution structure includes vias extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (ubm) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the ubm structures includes a first ubm layer including a first metal material or an alloy of the first metal material; and a second ubm layer between one of the bumps and the first ubm layer and including a second metal material.
