Samsung electronics co., ltd. (20240096403). MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME simplified abstract
Contents
MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME
Organization Name
Inventor(s)
Kangsub Jeong of Suwon-si (KR)
MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240096403 titled 'MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME
Simplified Explanation
The memory core circuit described in the abstract includes a memory cell array with sub cell arrays and a core control circuit with sub peripheral circuits. Each sub peripheral circuit extends underneath a corresponding sub cell array, with sub wordline drivers, bitline sense amplifiers, row decoding circuit, power circuit, and control circuit included in each sub peripheral circuit.
- Memory core circuit components:
- Memory cell array with sub cell arrays - Core control circuit with sub peripheral circuits - Sub wordline drivers - Bitline sense amplifiers - Row decoding circuit - Power circuit - Control circuit
Applications of this technology: This technology can be applied in various memory storage devices such as RAM, ROM, and flash memory, improving efficiency and reducing size.
Problems solved by this technology: This technology solves the problem of reducing the size of memory core circuits while enhancing design margins, leading to more efficient memory storage solutions.
Benefits of this technology: - Reduced size of memory core circuits - Enhanced design margins - Improved efficiency in memory storage devices
Potential commercial applications of this technology: "Efficient Memory Core Circuit Technology for Enhanced Storage Solutions"
Possible prior art: Prior art may include existing memory core circuit designs that do not utilize the cop structure to efficiently provide core control circuits.
Unanswered questions: 1. How does the cop structure specifically contribute to reducing the size of the memory core circuit? 2. Are there any potential drawbacks or limitations to implementing this technology in memory storage devices?
Original Abstract Submitted
a memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. each sub cell array includes memory cells respectively connected to wordlines and bitlines. each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. by using a cop structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.
