Samsung electronics co., ltd. (20240113003). SEMICONDUCTOR PACKAGE simplified abstract

SEMICONDUCTOR PACKAGE

Organization Name

samsung electronics co., ltd.

Inventor(s)

Yun Seok Choi of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240113003 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in the patent application consists of an upper substrate with a semiconductor chip, a buffer layer, a mold layer, through-electrodes, an interconnection layer, and bumps. The mold layer has a coefficient of thermal expansion greater than that of the upper substrate.

• Upper substrate with first and second surfaces
• Semiconductor chip on the first surface
• Buffer layer on the second surface
• Mold layer between the second surface and the buffer layer
• Through-electrodes penetrating the upper substrate and mold layer
• Interconnection layer connecting the semiconductor chip to the through-electrodes
• Bumps on the buffer layer connected to the through-electrodes

1. 1. 1. Potential Applications

- Advanced electronic devices - Semiconductor industry

1. 1. 1. Problems Solved

- Improved thermal expansion matching - Enhanced electrical connectivity

1. 1. 1. Benefits

- Better performance and reliability - Increased functionality

1. 1. 1. Potential Commercial Applications
         1. Enhanced Semiconductor Packaging Technology for Improved Performance

1. 1. 1. Possible Prior Art

No prior art known at this time.

1. 1. 1. 1. Unanswered Questions

1. 1. 1. 1. How does the coefficient of thermal expansion affect the overall performance of the semiconductor package?

The coefficient of thermal expansion of the mold layer plays a crucial role in preventing thermal stress and ensuring the reliability of the semiconductor package during temperature variations.

1. 1. 1. 1. What are the specific materials used in the mold layer to achieve the desired coefficient of thermal expansion?

The materials used in the mold layer must be carefully selected to meet the requirement of having a higher coefficient of thermal expansion compared to the upper substrate. Further research and development may be needed to optimize the material composition for better performance.

Original Abstract Submitted

a semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. the mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.