Samsung electronics co., ltd. (20240105267). NON-VOLATILE MEMORY DEVICE simplified abstract
Contents
- 1 NON-VOLATILE MEMORY DEVICE
NON-VOLATILE MEMORY DEVICE
Organization Name
Inventor(s)
Daeseok Byeon of Suwon-si (KR)
Beakhyung Cho of Suwon-si (KR)
NON-VOLATILE MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240105267 titled 'NON-VOLATILE MEMORY DEVICE
Simplified Explanation
The patent application describes a non-volatile memory device with a page buffer circuit that has a multi-stage structure, including high voltage and low voltage regions.
- The page buffer circuit includes a high voltage region, a first low voltage region, and a second low voltage region.
- The high voltage region consists of high voltage transistors connected to different bit lines.
- The low voltage regions each have a width corresponding to a pitch of bit lines.
- The structure allows for efficient data storage and retrieval in the memory device.
Potential Applications
This technology could be applied in:
- Solid-state drives
- Embedded systems
- Smartphones and tablets
Problems Solved
This technology helps in:
- Improving data storage efficiency
- Enhancing memory device performance
Benefits
The benefits of this technology include:
- Faster data access
- Higher data storage capacity
- Improved overall memory device reliability
Potential Commercial Applications
The potential commercial applications of this technology include:
- Memory chip manufacturing companies
- Consumer electronics manufacturers
- Data storage solution providers
Possible Prior Art
One possible prior art for this technology could be:
- Multi-stage memory buffer circuits in existing non-volatile memory devices
Unanswered Questions
How does this technology compare to traditional memory devices in terms of speed and efficiency?
This technology offers faster data access and improved storage efficiency compared to traditional memory devices.
What are the potential cost implications of implementing this technology in memory devices?
The cost implications of implementing this technology may include higher manufacturing costs initially, but could lead to cost savings in the long run due to improved efficiency and performance.
Original Abstract Submitted
provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. the high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.
