SK hynix Inc. patent applications published on September 21st, 2023

MEMORY DEVICE INCLUDING SELECT LINES (17944704)

Abstract

The present disclosure relates to a memory device including a first memory block including a first group of cell plugs and a second group of cell plugs, a second memory block including a third group of cell plugs and a fourth group of cell plugs, a connection region located between the first and second memory blocks, a first source select line commonly coupled to the first group of cell plugs and third group of cell plugs, a second source select line coupled to the second group of cell plugs, and a third source select line coupled to the fourth group of cell plugs.

Inventor

Yun Cheol HAN

MEMORY CONTROLLER AND OPERATING METHOD THEREOF (17984484)

Abstract

A memory controller includes a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index “M” among the plural write sequence indexes, and detect first data corresponding to a write sequence index “M−1” and second data corresponding to a write sequence index “M+1”; a barrier decision circuit configured to determine, based on whether first barrier information of the first data and second barrier information of the second data are identical with each other, whether a barrier request for the first data has been received from a host; and a data recovery operation determination circuit configured to determine whether to perform a recovery operation on target data corresponding to the write sequence index “M+1” and thereafter based on whether the barrier request for the first data has been received.

Inventor

Hye Mi KANG

MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME (17882112)

Abstract

A memory system may include a memory device including a plurality of memory areas each configured by a plurality of memory blocks; and a memory controller configured to generate zones each including at least one memory block selected from at least one of the memory areas included in the memory device, manage configuration information for each generated zone, sequentially store data from a first storage location of an open zone among the generated zones during a write operation on the open zone according to an external request, and determine a number of active target memory areas associated with the open zone on a basis of configuration information of the open zone.

Inventor

Dong Kyu LEE

STORAGE DEVICE AND OPERATING METHOD THEREOF (17878430)

Abstract

A storage device includes a nonvolatile memory device including a replay protected memory block; and a memory controller for, as a submission command requesting access to the replay protected memory block is received from an external host including a host memory having a plurality of Physical Region Pages (PRPs), acquiring a host replay protected memory block data frame stored in one of the plurality of PRPs and accessing the replay protected memory block. The submission command may include information on a position at which the memory controller is to store a response to the submission command among the plurality of PRPs.

Inventor

Byung Jun KIM

APPARATUS AND METHOD FOR TRANSFERING DATA IN MEMORY SYSTEM (17897766)

Abstract

A memory system includes: a memory device including a plurality of pages each including a plurality of L-level cells, K planes each including the plurality of pages, and N memory dies each including the K planes; and a controller suitable for dividing logical addresses corresponding to write data, into a plurality of divided logical groups by grouping the logical addresses by a preset number, when performing a program operation of transferring the write data to the memory device to store, and mapping each of the plurality of divided logical groups to a reference logical unit in a first order of bits of the L-level cell, a second order of the N memory dies, and a third order of the K planes, according to a size of the write data, in order to decide an order in which the write data are to be transferred to the memory device.

Inventor

Chan Hyeok CHO

DATA STORAGE DEVICE FOR DETERMINING A WRITE ADDRESS USING A NEURAL NETWORK (17889297)

Abstract

A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.

Inventor

Junhyeok JANG

MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD OF THE MEMORY SYSTEM FOR CONTROLLING GARBAGE COLLECTION (17849287)

Abstract

A memory system or memory controller may calculate a first data size, which is the sum of sizes of data requested to be written by write requests from outside the memory system after a first reference time point, calculate a second data size, which is the sum of sizes of data updated by the write requests among data already stored in the memory device from a second reference time point, and control execution of garbage collection on data stored in the memory device based on the first data size and the second data size.

Inventor

Gi Pyo UM

STACKED SEMICONDUCTOR DEVICE (17884963)

Abstract

A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.

Inventor

Jae Hyung PARK

SEMICONDUCTOR DEVICE (17737294)

Abstract

A semiconductor device includes: a first memory block having a first block pitch; and a second memory block belonging to a same plane as the first memory block, the second memory block located closer to a plane edge than the first memory block, the plane edge being an edge of the plane, wherein the second memory block has a second block pitch that is larger than the first block pitch.

Inventor

Jae Taek KIM

PAGE BUFFER CIRCUIT AND OPERATION METHOD THEREOF (17973988)

Abstract

A page buffer circuit may include: a data transfer circuit configured to transfer data, transferred to a first sensing node through a bit line, to a second sensing node during a data sensing operation; a first latch circuit configured to sense the data transferred to the first sensing node, and store the sensed data; and a second latch circuit configured to sense the data transferred to the second sensing node, and store the sensed data.

Inventor

Soo Yeol CHAI

DATA SAMPLING CIRCUIT AND DATA TRANSMITTER CIRCUIT (17847918)

Abstract

A data sampling circuit may include a pattern detection circuit configured to generate a slow signal by detecting a pattern of multibit data including input data, and a sampling circuit configured to sample the input data during an activation period of a sampling clock and having an operating speed of the sampling circuit reduced when the slow signal is activated.

Inventor

Inseok KONG

MEMORY AND OPERATION METHOD THEREOF (17980943)

Abstract

An operation method of a memory may include entering a self-refresh mode, increasing a level of a back-bias voltage in response to entering the self-refresh mode, performing self-refresh operations in a first cycle, confirming that the back-bias voltage reaches a level of a first threshold voltage, and performing the self-refresh operations in a second cycle longer than the first cycle in response to the confirmation.

Inventor

Woongrae KIM

INTERNAL VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME (18322409)

Abstract

An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

Inventor

Chan Hui JEONG

METHOD OF PROGRAMMING A SELECT TRANSISTOR OF A SEMICONDUCTOR MEMORY DEVICE (17879975)

Abstract

A semiconductor memory device includes a first cell string, a second cell string, a peripheral circuit, and a control logic. The first cell string includes first and second drain select transistors. The second cell string includes third and fourth drain select transistors. The peripheral circuit performs a program operation on the fourth drain select transistor included in the second cell string. The threshold voltage of the first drain select transistor is set through an ion implantation process. The threshold voltage of the fourth drain select transistor is set through the program operation.

Inventor

Hee Youl LEE

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE (17844965)

Abstract

A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform the program operation on the selected memory cells by using a first program voltage determined based on a first step voltage during a first program period and controls the peripheral circuit to perform the program operation on the selected memory cells by using a second program voltage determined based on a second step voltage different from the first step voltage during a second program period after the first program period.

Inventor

Eun Hye CHOI

MEMORY DEVICE (18095306)

Abstract

A memory device includes a plurality of memory cells, where each memory cell is configured to be in an erased state or one of a plurality of program states according to data stored therein. The memory device also includes a peripheral circuit configured to, in a program operation on the plurality of memory cells, perform a first program voltage application operation on first memory cells, the first memory cells being to be programmed to first respective program states. The peripheral circuit is also configured to perform, after the first program voltage application operation, a pre-program voltage application operation on second memory cells, the second memory cells being to be programmed to second respective program states.

Inventor

Hyun Seob SHIN

MEMORY DEVICE AND OPERATING METHOD THEREOF (17883719)

Abstract

A memory device includes a target memory block and a peripheral circuit configured to float local word lines which are coupled to the target memory block while an erase voltage rises to a target level, apply a first voltage to the local word lines after the erase voltage reaches the target level, and apply one or more group voltages to the local word lines after applying the first voltage.

Inventor

Cheol Joong PARK

DEVICE FOR DETERMINING READ REFERENCE VOLTAGE OF A MEMORY DEVICE AND OPERATING METHOD THEREOF (17847056)

Abstract

A device includes a threshold voltage distribution estimation network configured to generate an estimated distribution using a feature distribution and read trial information, a set of feature distributions generated from a plurality of threshold voltage distributions for a plurality of pages of a memory device, and a read reference voltage estimation network configured to generate a read reference voltage from the estimated distribution. The read trial information includes a read trial vector and an output value, the output value being generated by applying the read trial vector to a threshold voltage distribution for a page to be read among the plurality of threshold voltage distributions.

Inventor

Sunyoung JO

SEMICONDUCTOR MEMORY DEVICE MAINTAINING VERIFICATION DATA DURING PROGRAM SUSPEND, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE (17882295)

Abstract

A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.

Inventor

Yeong Jo MUN

REDUNDANCY MANAGING METHOD AND APPARATUS FOR SEMICONDUCTOR MEMORIES (17898126)

Abstract

A redundancy managing method and apparatus for semiconductor memories is disclosed. The redundancy managing method for semiconductor memories utilizes bitmap type storage by defining an appropriate storage space according to the type of a fault.

Inventor

Jong Sun PARK

SEMICONDUCTOR DEVICE INCLUDING THROUGH VIAS WITH DIFFERENT WIDTHS AND METHOD OF MANUFACTURING THE SAME (17962687)

Abstract

There is provided a semiconductor device including through vias and a method of manufacturing the same. The semiconductor device includes a substrate including a first via hole and a second via hole, a first through via formed in the first via hole, a second through via formed in the second via hole, an insulating layer first portion formed between a sidewall surface of the first via hole and the first through via, and an insulating layer second portion formed between a sidewall surface of the second via hole and the second through via. The insulating layer second portion is thinner than the insulating layer first portion, and the second through via is wider than the first through via,

Inventor

Jin Woong KIM

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE (18320818)

Abstract

There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.

Inventor

Jin Won LEE

MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE (17884289)

Abstract

There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a source line; a stack structure formed on the source line; a cell plug penetrating the stack structure and contacting the source line; a slit separating the stack structure; a source contact formed in the slit, the source contact in contact with the source line; and a compensation plug formed below the cell plug in the source line, wherein the compensation plug contains an impurity that has a higher concentration than an impurity that is contained in the source line.

Inventor

Chul Young KIM

SEMICONDUCTOR PACKAGES INCLUDING DAM PATTERNS AND METHODS FOR MANUFACTURING THE SAME (18323239)

Abstract

Disclosed are a semiconductor package and a manufacturing method thereof. Semiconductor chips may be disposed on a package substrate with vent holes formed therethrough, and a molding layer including a lower molding portion connected to an upper molding portion may be formed. The package substrate may include a substrate body with a plurality of unit regions, ball lands disposed in the unit regions, and first and second dam patterns that cross the unit regions and extend into edge regions, which is outside of the unit regions.

Inventor

Shin Young PARK

SEMICONDUCTOR PACKAGE HAVING ORDERED WIRE ARRANGEMENT BETWEEN DIFFERENTIAL PAIR CONNECTION PADS (17897863)

Abstract

A semiconductor package includes a package substrate, first and second semiconductor chips stacked on the package substrate and wire-bonded to the package substrate. The first semiconductor chip includes first differential pair signal pads, a first option signal pad, and a first signal path control circuit. The second semiconductor chip includes second differential pair signal pads, a second option signal pad, and a second signal path control circuit. The first signal path control circuit changes a signal path of one of the differential pair signals of the first semiconductor chip by a first control signal. The second signal path control circuit changes a signal path of one of the differential pair signals of the second semiconductor chip by a second control signal.

Inventor

Ki Yong LEE

IMAGE SENSING SYSTEM (17973989)

Abstract

Disclosed is an image sensing system including a first sub-pixel array having an arrangement of K×K pixels, where “K” is a natural number greater than 4, wherein the first sub-pixel array includes: first pixels disposed in a first diagonal direction and each having a green filter; second pixels disposed in a second diagonal direction that intersects the first diagonal direction and each having a red filter, and third pixels disposed in the second diagonal direction and each having a blue filter; and fourth pixels each having a white filter and disposed at the other positions except for arrangement positions of the first to third pixels disposed in the first and second diagonal directions, and fifth pixels suitable for measuring depth information, and the fourth pixels and the fifth pixels are disposed in a first pattern.

Inventor

Su Ram CHA

IMAGE SENSOR AND OPERATING METHOD THEREOF (17958525)

Abstract

Disclosed is an image sensor including a first sub-pixel array including a plurality of first pixel groups, which are respectively coupled to a plurality of first readout lines extending in a first direction and are adjacent to one another in a second direction intersecting the first direction; and a plurality of first switches suitable for selectively coupling a plurality of first floating diffusion nodes included in the plurality of first pixel groups, based on a plurality of first control signals.

Inventor

Min Kyu KIM

MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE (17884043)

Abstract

A memory device includes isolation layers and gate structures alternately stacked on a lower structure and a tunnel isolation layer penetrating the isolation layers and the gate structures. The memory device also includes a channel layer formed along an inner wall of the tunnel isolation layer and a core plug formed along an inner wall of the channel layer. Each of the gate structures includes: a floating gate surrounding an outer wall of the tunnel isolation layer; a first dielectric layer surrounding an outer wall of the floating gate; a second dielectric layer surrounding an outer wall of the first dielectric layer; a third dielectric layer surrounding an outer wall of the second dielectric layer; and a gate line formed between the isolation layers, the gate line filling a region surrounded at least in part by the third dielectric layer.

Inventor

Yun Cheol HAN

MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE (17874849)

Abstract

There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a source structure; and a stack structure over the source structure, the stack structure including a plug and a slit, wherein the slit includes a source contact being connected to the source structure.

Inventor

Chul Young KIM

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE (17891655)

Abstract

There are provided a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a plurality of channel structures penetrating the gate structure, the plurality of channel structures being arranged in a first direction; a plurality of cutting structures each isolating each of the plurality of channel structures, respectively, into a plurality of divided channel structures while penetrating each of the plurality of channel structures, respectively; and a plurality of interconnection lines located over the gate structure and extending in the first direction. Each of the plurality of cutting structures has substantially a cross (+) shape including extension parts extending in directions oblique to the first direction.

Inventor

Sung Wook JUNG

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE (17895398)

Abstract

A semiconductor device, and a method of manufacturing the semiconductor device, includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; at least one channel structure penetrating the gate structure, the at least one channel structure being aligned in a first direction; a first cutting structure extending in the first direction, the first cutting structure penetrating the at least one channel structure; a contact pad in contact with an upper surface of the at least one channel structure, the contact pad having a critical dimension greater than a critical dimension of the upper surface of the at least one channel structure; and a second cutting structure in contact with an upper surface of the first cutting structure and penetrating the contact pad.

Inventor

Won Geun CHOI

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE (17943427)

Abstract

There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of conductive patterns and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; a plurality of channel structures extending in a first direction substantially perpendicular to the substrate to penetrate the stack structure; at least one first slit extending in a second direction substantially horizontal to the substrate while penetrating conductive patterns for select lines among the plurality of conductive patterns; a second slit extending in the second direction while penetrating the conductive patterns for select lines; and a plurality of support structures disposed on a bottom of the second slit, the plurality of support structures penetrating conductive patterns for word lines among the plurality of conductive patterns.

Inventor

Kun Young LEE

SEMICONDUCTOR MEMORY DEVICE (17949485)

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a source structure, a first drain select line spaced apart from the source structure, first to fourth bit lines of a first group of bit lines spaced apart from the first drain select line, first to fourth channel structures of a first column of channel structures extending from the source structure to pass through the first drain select line, and first to fourth contact plugs of the first contact group of contact plugs connecting the first to fourth channel structures of the first column of channel structures to the first to fourth bit lines of the first group of bit lines, respectively, and in which each of the first to fourth channel structures of the first column of channel structures extend to overlap the first to fourth bit lines of the first group of bit lines.

Inventor

Sang Hyon KWAK

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (17973236)

Abstract

A three-dimensional (3D) semiconductor device includes a plurality of stack structures, a plurality of channel plugs, a slit structure and a plurality of dummy channel plugs. The stack structures include at least two conductive layers and at least two insulation layers, each being alternately stacked. The channel plugs are vertically formed through the stack structure. The slit structure is arranged at one side of the stack structure. The plurality of dummy channel plugs is arranged in the stack structures to be adjacent to the slit structure. Each of the channel plugs includes a channel insulation layer and a channel layer. Each of the dummy channel plugs includes at least one of the channel insulation layer, the channel layer, and a material of the plurality of conductive layers.

Inventor

Sung Wook JUNG

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (18085365)

Abstract

A three-dimensional (3D) semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a conductive pattern and a second insulation pattern. The conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be configured to physically contact an upper surface of the conductive pattern. The second insulation pattern may have a property different from a property of the first insulation pattern. The vertical channel structure may be formed through the stack structure.

Inventor

Jung Ryul AHN

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE THREE-DIMENSIONAL SEMICONDUCTOR DEVICE (18085366)

Abstract

A 3D semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a lower conductive pattern and a second insulation pattern. The lower conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be arranged on the lower conductive pattern. The first insulation pattern may have a thickness thicker than a thickness of the second insulation pattern. The vertical channel structure may be arranged in the stack structure. The lower conductive pattern may have an upper surface directly in contact with a lower surface of the second insulation pattern.

Inventor

Seung Min LEE

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE THREE-DIMENSIONAL SEMICONDUCTOR DEVICE (18085421)

Abstract

A three-dimeiisioiial semiconductor device including a memory block including a stack structure comprising a second sub stack formed over a first sub stack, a plurality of channel plugs formed through the stack structure, and a separation pattern formed in the memory block.

Inventor

Seung Min LEE

MAGNETIC MEMORY DEVICE (17943151)

Abstract

According to one embodiment, a magnetic: memory device includes a stacked structure in which a magnetoresistance effect element and a switching element are stacked. The switching element is provided on a lower layer side of the magnetoresistance effect element, and when viewed in a stacking direction of the magnetoresistance effect element and the switching element, a pattern of the switching element is located inside a pattern of the magnetoresistance effect element.

Inventor

Kenichi YOSHINO

SEMICONDUCTOR DEVICE INCLUDING HEAT INSULATING LAYER AND METHOD OF MANUFACTURING THE SAME (17894332)

Abstract

Disclosed semiconductor devices include a substrate, a device pattern structure disposed over the substrate, and a heat insulating layer disposed on the device pattern structure. The device pattern structure includes metal-organic frameworks.

Inventor

Won Tae KOO