SK hynix Inc. patent applications on April 11th, 2024
Patent Applications by SK hynix Inc. on April 11th, 2024
SK hynix Inc.: 31 patent applications
SK hynix Inc. has applied for patents in the areas of H10B43/27 (6), H10B41/27 (6), H01L23/528 (5), G06F12/06 (4), H03K5/24 (4)
With keywords such as: device, data, memory, circuit, signal, line, configured, electronic, control, and test in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Gyeong Ho HYUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G01R31/26
Abstract: a test device may include a test memory device, an insulation layer and a charge injection electrode. the test memory device may include a memory layer and a gate electrode layer on a semiconductor substrate. the insulation layer may be arranged on the test memory device. the charge injection electrode may be arranged on the insulation layer to inject a charge into the test memory device based on a voltage.
Inventor(s): YU-AN CHEN of Zhubei City Hsinchu County (TW) for sk hynix inc., NY-WEN SHEU of Zhubei City Hsinchu County (TW) for sk hynix inc.
IPC Code(s): G01R31/317
Abstract: system, method for circuit validation, and system and method for facilitating circuit validation are provided. the circuit validation system comprises a prototype system and a computing device. the prototype system comprises a programming logic device circuit configured to implement a modified circuit design. the modified circuit design includes a circuit module as a design under test (dut), an input generation circuit coupled to the circuit module for outputting input signals to the circuit module in response to a test signal, and an output acquisition circuit coupled to the circuit module for storing output data from the circuit module. the computing device is capable of being coupled to the prototype system and configured to generate the test signal to perform a test of the dut on the prototype system.
20240118399.IMAGE SENSOR RELATED TO MEASURING DISTANCE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Hyung JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G01S7/4914, G01S17/36, G01S17/894, H04N25/771, H04N25/79
Abstract: an image sensor includes: a unit pixel configured to output pixel data in response to a drive signal being input to the unit pixel; and a control circuit configured to provide the unit pixel with a first drive signal and a second drive signal each having a first phase, and a third drive signal having a second phase with a phase difference of 180 degrees with respect to the first phase in a first mode, the control circuit providing the unit pixel with the first drive signal having the first phase, the second drive signal having the second phase, and the third drive signal having a deactivation voltage in a second mode.
Inventor(s): Ji Hoon SEOK of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F12/02
Abstract: a memory system includes a memory device and a controller. the memory device includes a plurality of memory cells. the controller is configured to select first map data entries associated with first data entries stored in a first region of the memory device that includes some of the plurality of memory cells, to exclude a second map data entry associated with second data entry sequentially read from among the first map data entries, and to transmit a remaining first map data entry to an external device.
20240118810.MEMORY SYSTEM AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Moon Hyeok CHOI of Gyeonggi-do (KR) for sk hynix inc., Kwang Ho CHOI of Gyeonggi-do (KR) for sk hynix inc., Nam Hyeok JEONG of Gyeonggi-do (KR) for sk hynix inc., Yong Wan HWANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a memory system may include: a memory device configured to store first training information and second training information representing different training patterns; and a memory controller configured to: perform a first training operation on the memory device based on the first training information, and perform, when a result of the first training operation is out of a predetermined range, a second training operation on the memory device plural times based on the second training information.
Inventor(s): Dong Uk LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hae Chang YANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hun Wook LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
Abstract: a semiconductor memory device and a method of operating the semiconductor memory device are provided. the semiconductor memory device includes a memory block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation on the memory block, and control logic configured to control the peripheral circuit to perform the program operation on the memory block, wherein the program operation comprises programming to program normal data to a first sub-block, allocated to be a normal sub-block, among the plurality of sub-blocks, and programming parity data of the normal data to a second sub-block, allocated to be a backup block, among the plurality of sub-blocks.
20240118839.MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM_simplified_abstract_(sk hynix inc.)
Inventor(s): Jeong Hyun KIM of Gyeonggi-do (KR) for sk hynix inc., Ji Hun CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F11/14, G06F11/07
Abstract: according to embodiments of the present disclosure, there may be provided a memory system and an operating method thereof, including a host accessible area accessible directly from an external device, transmitting information on the host accessible area to an external memory, receiving a direct memory access request generated based on the information for the host accessible area from the external device according to an urgent event, and providing the external device with a direct memory access to the host accessible area in response to the direct memory access request.
Inventor(s): Seong Ju LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Choung Ki SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F5/01
Abstract: a shift array circuit generates output data having the number of bits greater than the number of bits of target data by shifting the target data by a bit corresponding to a value of shift data. the shift array circuit includes a plurality of shift arrays. the plurality of shift arrays is configured to receive bits of the shift data for each bit and each configured to perform a shift operation on input data that is input to each of the plurality of shift arrays by a shift bit corresponding to an input bit, among the bits of the shift data.
Inventor(s): WEN JYH LIN of Zhubei City Hsinchu County (TW) for sk hynix inc.
IPC Code(s): G06F11/14, H04L1/16
Abstract: a method for facilitating frame error handling and an electronic device are provided. the method is for use in an electronic device capable of communicating with another electronic device. the method comprises the following. in response to an error event in an advanced line encoding mode, closing a first burst transmission and opening a second burst transmission are performed, wherein the advanced line encoding mode indicates that the electronic device is capable of data transmission by using an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding. a lane alignment pattern is transmitted in the advanced line encoding mode from the electronic device to the other electronic device after the second burst transmission is opened. a negative acknowledgement control frame is transmitted in the advanced line encoding mode from the electronic device to the other electronic device after the lane alignment pattern is transmitted.
Inventor(s): WEN JYH LIN of Zhubei City Hsinchu County (TW) for sk hynix inc.
IPC Code(s): G06F11/22, G06F11/263
Abstract: method for facilitating testing for an interconnection protocol, a controller, and an electronic device are provided. the method is suitable for an electronic device capable of communicating with another electronic device. the method comprises the following steps. at a controller of the electronic device, a test mode request signal is received to enter a test mode in which data transmission is to be performed by using an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding. at the controller, a test data signal is generated to indicate a test pattern including an ordered set portion and a data pattern portion by using the advanced line encoding. the test data signal is transmitted according to the advanced line encoding through the electronic device to the other electronic device.
Inventor(s): Dae Sung KIM of Icheon-si (KR) for sk hynix inc., Bi Woong CHUNG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F12/06
Abstract: a decoding device may determine a candidate data unit among a plurality of data units included in one data chunk, in parallel with an operation of decoding a target data unit among the plurality of data units. the decoding device may determine whether to decode the candidate data unit, and may decode the candidate data unit according to whether to decode the candidate data unit, after executing decoding on the target data unit.
Inventor(s): Dae Sung KIM of Icheon-si (KR) for sk hynix inc., Bi Woong CHUNG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F12/06
Abstract: a decoding device may determine a candidate data unit among a plurality of data units included in one data chunk, in parallel with an operation of decoding a target data unit among the plurality of data units. the decoding device may determine whether to decode the candidate data unit, and may decode the candidate data unit according to whether to decode the candidate data unit, after executing decoding on the target data unit.
20240119986.MEMORY DEVICE AND MEMORY SYSTEM_simplified_abstract_(sk hynix inc.)
Inventor(s): Minseong KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G11C11/4072
Abstract: a memory device includes a memory cell array including a plurality of rows; a time table including a plurality of fields respectively corresponding to the rows; and a refresh control circuit configured to read field data from a k-th field of the time table according to an access command for a k-th row among the rows, where k is a natural number, determine whether to issue a refresh request signal for the k-th row based on current clock data and the field data, and update the field data of the k-th field using the current clock data.
20240119994.VERTICAL MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Seung-Hwan KIM of Seoul (KR) for sk hynix inc., Su-Ock CHUNG of Seoul (KR) for sk hynix inc., Seon-Yong CHA of Chungcheongbuk-do (KR) for sk hynix inc.
IPC Code(s): G11C11/408, H01L23/528, H10B12/00
Abstract: a memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.
Inventor(s): Won Ha CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4093, H01L23/00, H01L23/49, H01L23/522, H01L25/16
Abstract: a single memory package includes a package substrate; at least one of a memory chip and a buffer chip mounted on the package substrate; m�n number of interface data channel buses between the memory chip and the buffer chip; and (m�n)/2number of outer data channel buses connected to the buffer chip. the buffer chip receives data from the memory chip through the interface data channel buses, and provides the data through the outer data channel buses. the m, n, and n are natural numbers.
Inventor(s): Hyung Jin CHOI of Gyeonggi-do (KR) for sk hynix inc., Chan Hui JEONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/24, G11C16/26, G11C16/34
Abstract: an operating method of a non-volatile memory device includes simultaneously performing a program operation on a plurality of selection transistors included in a plurality of cell strings each including a corresponding selection transistor of the selection transistors and a plurality of memory cells, each of the cell strings being coupled between a common source line and a corresponding bit line of a plurality of bit lines; sequentially performing verification operations on respective groups of the selection transistors, the groups being coupled to respective selection lines; and sequentially storing results of the verification operations into respective data latch circuits within each of a plurality of page buffers coupled to the bit lines.
Inventor(s): Suk Hwan CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/12, G11C29/18, G11C29/46
Abstract: the present technology may include: a current mirror configured to apply a test current that is generated by a test voltage to a selected word line, among a plurality of word lines, and to generate a copy current by copying the test current; a comparison circuit configured to compare at least one reference current with the copy current to generate a comparison result signal; and a test control circuit configured to perform a first noise control mode that charges unselected word lines, among the plurality of word lines, with electric charges, in response to a test mode signal and floats the unselected word lines.
20240120015.SEMICONDUCTOR DEVICE AND METHOD FOR PERFORMING TEST_simplified_abstract_(sk hynix inc.)
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/14, G11C29/02, G11C29/12
Abstract: a semiconductor device includes a self-test circuit configured to generate an internal clock having a higher frequency than a clock applied from a device external to the semiconductor device, to generate an instruction signal from a pre-instruction signal extracted through a data line, and to generate an internal control signal from the instruction signal. the semiconductor device also includes a command control circuit configured to generate a test command to perform a self-test for determining whether a defect has occurred in first memory cells and second memory cells based on the internal clock and the internal control signal. the semiconductor device further includes a data control circuit configured to output data stored in the first memory cells based on the test command, and to store data output from the first memory cells in the second memory cells.
Inventor(s): Byung Wook BAE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Ryul AHN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/54
Abstract: a memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. the second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.
20240120275.METAL WIRING OF SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Seong Ho CHOI of Icheon-si (KR) for sk hynix inc., Chang Man SON of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L23/528, H01L21/768, H01L23/532
Abstract: a metal wiring of a semiconductor device may include: a first metal line disposed in a first metal layer, and defined with an opening in a first region; and a contact metal passing through a dielectric layer under the first metal layer adjacent to the opening and connected to the first metal line around the opening.
Inventor(s): Bok Gyu MIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Beom Sang CHO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/544, H01L25/065
Abstract: a substrate includes: a first die alignment mark and a first die position mark defining a die stack region. the first die alignment mark has substantially a cross shape having substantially a vertical bar and substantially a horizontal bar intersecting each other substantially perpendicularly, and the first die position mark includes a first main position mark having a first area and a first branch position mark having a second area different from the first area.
20240120292.STACK PACKAGE INCLUDING INSERT DIE FOR REINFORCEMENT_simplified_abstract_(sk hynix inc.)
Inventor(s): Jin Woong KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jong Yeon KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00, H01L23/48
Abstract: a stack package includes a first die stack including first dies, a second die stack including second dies, and an insert die between the first die stack and the second die stack, wherein the insert die is thicker than each of the first and second dies.
Inventor(s): Yeonsu JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Woongrae KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Min YOON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03F3/04, H03K5/24
Abstract: a sensing and amplifying circuit includes a driving voltage control circuit configured to control a voltage level of a driving voltage based on a surrounding temperature of the sensing and amplifying circuit, a delay control circuit configured to generate a line connection signal and an inverted line connection signal in response to a delay start signal by being supplied with the driving voltage, and a sense amplifier configured to perform a sensing and amplifying operation in response to the line connection signal and the inverted line connection signal. an interval between enable timing of the line connection signal and enable timing of the inverted line connection signal is adjusted as the surrounding temperature changes.
Inventor(s): Dong Seok KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Joo Won OH of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Keun Jin CHANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03H11/28, G05F1/56, H03K5/24
Abstract: a semiconductor device includes an on-die resistor circuit comprising an on-die resistor, a calibration circuit configured to perform a calibration operation on the on-die resistor, and a calibration control circuit configured to control the calibration operation of the calibration circuit. the calibration circuit includes a current generating circuit configured to supply a calibration current to the on-die resistor and a comparing circuit configured to compare the magnitude of a first input signal that is generated by the calibration current and the on-die resistor with a magnitude of a second input signal that is generated by the calibration current and an external resistor.
Inventor(s): LAN FENG WANG of Zhubei City Hsinchu County (TW) for sk hynix inc., WEN JYH LIN of Zhubei City Hsinchu County (TW) for sk hynix inc.
IPC Code(s): H04L69/04, H04L27/04
Abstract: method for control protocol frame transmission and electronic device are provided. the method comprises following operations. by the electronic device operating in an advanced line encoding mode and having a first burst from the electronic device to the other electronic device, the first burst is closed and a second burst is opened from the electronic device to the other electronic device for request frame transmission, wherein the electronic device operating in the advanced line encoding mode is configured to transmit data by using an advanced line encoding having an effective data rate larger than an effective data rate of 8b/10b encoding. by the electronic device, a request frame is transmitted in the second burst.
Inventor(s): WEN JYH LIN of Zhubei City Hsinchu County (TW) for sk hynix inc.
IPC Code(s): H04L69/22, H04L69/08
Abstract: electronic device and operation method for an electronic device are provided. in the electronic device, a specific number of protocol data units (pdus) are received as a pdu block to be transmitted. the pdu block includes at least one pdu belonging to a control pdu category. a control block is generated according to the pdu block by reordering, wherein the control block includes a header being placed before all pdus of the pdu block and indicating a control block category; in the control block, any pdu belonging to the control pdu category in the pdu block is placed after the header and before any pdu belonging to a data pdu category in the pdu block. the control block is transmitted through the electronic device to another electronic device according to an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding.
Inventor(s): Jae Man YOON of Gyeonggi-do (KR) for sk hynix inc., Jin Hwan JEON of Gyeonggi-do (KR) for sk hynix inc., Tae Kyun KIM of Gyeonggi-do (KR) for sk hynix inc., Jung Woo PARK of Gyeonggi-do (KR) for sk hynix inc., Su Ock CHUNG of Gyeonggi-do (KR) for sk hynix inc., Jae Won HA of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
Abstract: a semiconductor device and a method of fabricating the same are provided. according to the present invention, a semiconductor device comprises an active region formed in a substrate, and including flat surfaces and hole-shaped recess portions; upper-level plugs disposed over the flat surfaces; a spacer disposed between the upper-level plugs and providing a trench exposing the hole-shaped recess portions; a lower-level plug filling the hole-shaped recess portions; and a buried conductive line disposed over the lower-level plug and partially filling the trench.
Inventor(s): Jae Ho KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B20/00, H01L23/528
Abstract: a semiconductor device includes: a source structure comprising a cell area and an edge area; a stack located on the edge area of the source structure; a gate structure located on the cell area of the source structure; a channel structure connected to the cell area of the source structure by extending through the gate structure; and a read-only memory area.
Inventor(s): Nam Jae LEE of Cheongju-si Chungcheongbuk-do (KR) for sk hynix inc.
IPC Code(s): H10B41/27, H01L21/225, H01L21/324, H10B43/27, H10B63/00
Abstract: a method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.
Inventor(s): Jong Gi KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Young Jin NOH of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae O PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jin Ho BIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dong Chul YOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Yoo Il JEON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B43/10
Abstract: a manufacturing method of a semiconductor device may include: forming a stack comprising first material layers and second material layers that are alternately stacked; forming an opening in the stack; forming a first seed layer in the opening; forming a first buffer layer by surface-treating the first seed layer; and forming a blocking layer by oxidizing the first seed layer through the first buffer layer.
Inventor(s): Rho Gyu KWAK of Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Gyeonggi-do (KR) for sk hynix inc., Seok Min CHOI of Gyeonggi-do (KR) for sk hynix inc., Won Geun CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27
Abstract: a semiconductor device may include: first insulating pillars arranged in a first direction; second insulating pillars arranged alternately with the first insulating pillars and having a first width in the first direction and a second width in a second direction intersecting the first direction, the first width being greater than the second width; first memory cells located between the second insulating pillars and stacked along a first sidewall of each of the first insulating pillars; and second memory cells located between the second insulating pillars and stacked along a second sidewall of each of the first insulating pillars.
- SK hynix Inc.
- G01R31/26
- Sk hynix inc.
- G01R31/317
- G01S7/4914
- G01S17/36
- G01S17/894
- H04N25/771
- H04N25/79
- G06F3/06
- G06F12/02
- G06F11/14
- G06F11/07
- G06F5/01
- H04L1/16
- G06F11/22
- G06F11/263
- G06F12/06
- G11C11/406
- G11C11/4072
- G11C11/408
- H01L23/528
- H10B12/00
- G11C11/4093
- H01L23/00
- H01L23/49
- H01L23/522
- H01L25/16
- G11C16/10
- G11C16/24
- G11C16/26
- G11C16/34
- G11C29/12
- G11C29/18
- G11C29/46
- G11C29/14
- G11C29/02
- G11C29/54
- H01L21/768
- H01L23/532
- H01L23/544
- H01L25/065
- H01L23/48
- H03F3/04
- H03K5/24
- H03H11/28
- G05F1/56
- H04L69/04
- H04L27/04
- H04L69/22
- H04L69/08
- H10B20/00
- H10B41/27
- H01L21/225
- H01L21/324
- H10B43/27
- H10B63/00
- H10B41/10
- H10B43/10
