SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME: abstract simplified (17885081)

• This abstract for appeared for patent application number 17885081 Titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME'

Simplified Explanation

This abstract describes a semiconductor memory device that includes two main circuits: a row hammer management circuit and a refresh control circuit.

The row hammer management circuit keeps track of the number of times each memory cell row is accessed and stores this count data in count cells for each row. It also has a hammer address queue that stores addresses of memory cells that are being accessed frequently. When the number of these candidate hammer addresses reaches a certain threshold (second number), it changes the logic level of an error signal sent to the memory controller. When the number of candidate hammer addresses reaches another threshold (first number), it outputs one of the candidate addresses as a hammer address.

The refresh control circuit is responsible for performing a hammer refresh operation on memory cell rows that are physically adjacent to the memory cell row corresponding to the hammer address. This operation helps prevent the row hammer effect, which is a phenomenon where repeated accessing of certain memory cells can cause data corruption in nearby cells.

In summary, this memory device has a circuit that keeps track of frequently accessed memory cell rows and triggers a refresh operation on neighboring rows to prevent data corruption.

Original Abstract Submitted

A semiconductor memory device includes a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access on each memory cell row to store the counted values in count cells of each memory cell row as count data. A hammer address queue in the row hammer management circuit stores candidate hammer addresses, which are intensively accessed, in response to a number of the candidate hammer addresses reaching a second number, transitions a logic level of an error signal provided to the memory controller, and, in response to the number of the candidate hammer addresses reaching the first number, outputs one of the candidate hammer addresses as a hammer address. The refresh control circuit performs a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.