SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION: abstract simplified (18333886)

• This abstract for appeared for patent application number 18333886 Titled 'SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION'

Simplified Explanation

The abstract describes a semiconductor device that consists of multiple layers stacked on top of each other. There is a channel structure that runs through these layers. The lower stack structure has two layers of electrodes - one near the interface with the upper stack structure and another in the center. Similarly, the upper stack structure also has two layers of electrodes. The thickness of the first electrode layer in either the lower or upper stack structure is greater than the second electrode layer. Additionally, there is at least one insulating layer between the first electrode layers.

Original Abstract Submitted

A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.