Qualcomm incorporated (20240121073). REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP simplified abstract
Contents
- 1 REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.10.1 How does the calibration circuit ensure accurate calibration of both the delay-locked loop and the clock and data recovery circuit?
- 1.10.2 What are the specific parameters or metrics used to determine the effectiveness of the calibration process in optimizing the performance of the data communication interface?
- 1.11 Original Abstract Submitted
REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP
Organization Name
Inventor(s)
REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240121073 titled 'REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP
Simplified Explanation
The patent application describes a data communication interface with a delay-locked loop, phase interpolator, clock and data recovery circuit, and calibration circuit. The delay-locked loop generates a receive clock signal based on timing information from a clock channel, the phase interpolator provides a phase-shifted clock signal based on transitions in a data signal, the clock and data recovery circuit captures data using the phase-shifted clock signal, and the calibration circuit calibrates both the delay-locked loop and the clock and data recovery circuit.
- The delay-locked loop generates a receive clock signal based on timing information from a clock channel.
- The phase interpolator provides a phase-shifted clock signal based on transitions in a data signal.
- The clock and data recovery circuit captures data using the phase-shifted clock signal.
- The calibration circuit calibrates the delay-locked loop and the clock and data recovery circuit.
Potential Applications
This technology can be applied in high-speed data communication systems, such as in networking equipment, telecommunications devices, and data centers.
Problems Solved
1. Synchronization of data signals with clock signals in data communication links. 2. Ensuring accurate data capture and recovery in high-speed communication systems.
Benefits
1. Improved data transmission reliability. 2. Enhanced signal integrity. 3. Higher data transfer speeds.
Potential Commercial Applications
Optimized Clock and Data Recovery Circuit for High-Speed Data Communication Systems
Possible Prior Art
Prior art may include patents or publications related to delay-locked loops, phase interpolators, clock and data recovery circuits, and calibration circuits in data communication interfaces.
Unanswered Questions
How does the calibration circuit ensure accurate calibration of both the delay-locked loop and the clock and data recovery circuit?
The patent application mentions the calibration process but does not provide specific details on the methodology used for calibration.
What are the specific parameters or metrics used to determine the effectiveness of the calibration process in optimizing the performance of the data communication interface?
The patent application does not elaborate on the specific criteria or measurements used to evaluate the success of the calibration process in improving the functionality of the interface.
Original Abstract Submitted
a data communication interface has a delay-locked loop configured to generate a receive clock signal based on timing information provided by a signal received over a clock channel of a data communication link, a phase interpolator configured to provide a phase-shifted clock signal by phase-shifting one or more edges in the receive clock signal based on timing of transitions in a data signal received over a data channel of the data communication link, a clock and data recovery circuit configured to capture data from the data signal using the phase-shifted clock signal, and a calibration circuit. the calibration circuit is configured to calibrate the delay-locked loop while the clock and data recovery circuit is in an idle state, recalibrate the delay-locked loop when the clock and data recovery circuit is activated, and calibrate the clock and data recovery circuit after recalibrating the delay-locked loop.
