Qualcomm incorporated (20240105243). CLOCK QUALIFIER ENHANCEMENT FOR EXTERNAL DOUBLE DATA RATE MEMORY INTERFACES simplified abstract

CLOCK QUALIFIER ENHANCEMENT FOR EXTERNAL DOUBLE DATA RATE MEMORY INTERFACES

Organization Name

qualcomm incorporated

Inventor(s)

Yong Xu of San Diego CA (US)

Satish Krishnamoorthy of San Diego CA (US)

Boris Dimitrov Andreev of San Diego CA (US)

Patrick Isakanian of El Dorado Hills CA (US)

Farrukh Aquil of San Diego CA (US)

Vikas Mahendiyan of San Diego CA (US)

Ravindra Arvind Khedkar of San Diego CA (US)

CLOCK QUALIFIER ENHANCEMENT FOR EXTERNAL DOUBLE DATA RATE MEMORY INTERFACES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240105243 titled 'CLOCK QUALIFIER ENHANCEMENT FOR EXTERNAL DOUBLE DATA RATE MEMORY INTERFACES

Simplified Explanation

The memory interface circuit described in the abstract is designed to receive and process data signals in a memory system. Here is a simplified explanation of the patent application:

• The circuit includes multiple differential receivers to handle different types of signals.
• The first receiver is connected to a reference voltage source.
• The second receiver receives a differential data strobe signal in complementary signals.
• The third receiver is connected to a different reference voltage source and one of the complementary signals.
• A clock generation circuit generates a read clock signal based on the second receiver's output.
• A qualifying signal from the third receiver is used to qualify edges in the read clock signal.
• A data capture circuit captures data from the first receiver based on the edges in the read clock signal.

Potential Applications: - Memory systems - Data processing systems - Communication systems

Problems Solved: - Efficient data signal processing - Accurate clock signal generation - Reliable data capture

Benefits: - Improved data transfer speeds - Enhanced signal integrity - Reduced errors in data processing

Potential Commercial Applications:

1. 1. 1. Optimizing Data Transfer in Memory Systems

Possible Prior Art: There may be prior art related to memory interface circuits, differential receivers, clock generation circuits, and data capture circuits in the field of memory systems and data processing technologies.

Unanswered Questions:

1. 1. 1. How does the circuit handle signal noise and interference?

The abstract does not provide details on how the circuit mitigates signal noise and interference to ensure accurate data processing.

1. 1. 1. What is the power consumption of the memory interface circuit?

The abstract does not mention the power consumption of the circuit, which is crucial for evaluating its efficiency and practicality in real-world applications.

Original Abstract Submitted

a memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.