Qualcomm incorporated (20240097689). SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS simplified abstract
Contents
- 1 SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS
Organization Name
Inventor(s)
Jianjun Yu of San Diego CA (US)
Tomas O'sullivan of San Diego CA (US)
Razak Hossain of San Diego CA (US)
Lai Kan Leung of San Marcos CA (US)
SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240097689 titled 'SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS
Simplified Explanation
The present disclosure relates to techniques for synchronizing phase-locked loop (PLL) circuits. The method involves obtaining an indication to perform a synchronizing action at two PLL circuits and then performing the synchronizing action in response to the indication.
- Synchronizing action performed at first and second PLL circuits
- Indication triggers the synchronizing action
Potential Applications
The technology can be applied in various fields such as telecommunications, networking, and signal processing where precise synchronization of PLL circuits is crucial.
Problems Solved
1. Ensures accurate synchronization between multiple PLL circuits 2. Improves overall system performance by reducing phase discrepancies
Benefits
1. Enhanced system reliability and stability 2. Minimized phase errors and jitter 3. Simplified operation and maintenance of PLL circuits
Potential Commercial Applications
Optimizing synchronization in 5G networks Improving signal processing in radar systems
Possible Prior Art
One possible prior art could be the use of external clock sources to synchronize PLL circuits in communication systems.
What are the limitations of the proposed synchronization technique?
The article does not mention any potential limitations of the proposed synchronization technique.
How does this innovation compare to existing methods of synchronizing PLL circuits?
The article does not provide a direct comparison to existing methods of synchronizing PLL circuits.
Original Abstract Submitted
aspects of the present disclosure provide techniques and apparatus for synchronizing phase-locked loop (pll) circuits. an example method of operating pll circuits includes obtaining an indication to perform a synchronizing action at a first pll circuit and a second pll circuit; and performing the synchronizing action at the first pll circuit and the second pll circuit in response to obtaining the indication.
