Qualcomm incorporated (20240096964). VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS simplified abstract
Contents
- 1 VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this technology compare to existing methods for reducing contact resistance and parasitic capacitance in field-effect transistors?
- 1.11 What are the specific manufacturing processes involved in implementing these innovations in VCFETs?
- 1.12 Original Abstract Submitted
VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS
Organization Name
Inventor(s)
Junjing Bao of San Diego CA (US)
Giridhar Nallapati of San Diego CA (US)
VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240096964 titled 'VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS
Simplified Explanation
The patent application describes vertical channel field-effect transistors (VCFETs) with reduced contact resistance and/or parasitic capacitance, along with related fabrication methods.
- The end portion of the vertical channel has a semiconductor structure with an expanded width in the horizontal direction parallel to the substrate surface, providing a larger area for forming a contact for a source/drain to reduce contact resistance.
- The spacer includes one or more air gaps to form an air spacer(s) between the gate and the contact, reducing the overall average permittivity of the spacer and thus reducing parasitic capacitance.
- In one example, the air spacer(s) of the VCFET is elongated in the horizontal direction parallel to the substrate surface to further decrease parasitic capacitance.
Potential Applications
This technology could be applied in the semiconductor industry for improving the performance of vertical channel field-effect transistors by reducing contact resistance and parasitic capacitance.
Problems Solved
This innovation addresses the issues of high contact resistance and parasitic capacitance in vertical channel field-effect transistors, which can limit their efficiency and speed.
Benefits
The benefits of this technology include improved performance and efficiency of VCFETs, leading to better overall functionality in electronic devices.
Potential Commercial Applications
With its ability to enhance the performance of VCFETs, this technology could find applications in various electronic devices, such as smartphones, computers, and other semiconductor-based products.
Possible Prior Art
One possible prior art in this field could be the use of different materials or structures to reduce contact resistance and parasitic capacitance in field-effect transistors.
Unanswered Questions
How does this technology compare to existing methods for reducing contact resistance and parasitic capacitance in field-effect transistors?
The article does not provide a direct comparison with existing methods or technologies in the field.
What are the specific manufacturing processes involved in implementing these innovations in VCFETs?
The article does not delve into the detailed manufacturing processes required to incorporate these improvements in VCFETs.
Original Abstract Submitted
vertical channel field-effect transistors (vcfets) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods. in exemplary aspects, to reduce contact resistance of the vcfet, an end portion of the vertical channel has a semiconductor structure that has an expanded width in the horizontal direction parallel to the substrate surface. this provides a greater area to form a contact for a source/drain to reduce contact resistance of the vcfet. to reduce the parasitic capacitance between the gate and a contact of the vcfet, the spacer includes one or more air gaps that form an air spacer(s) between the gate and the contact to reduce the overall average permittivity of the spacer. in one example, the air spacer(s) of the vcfet is elongated in the horizontal direction parallel to the substrate surface (and perpendicular to the vertical direction of the vertical channel) to further reduce the parasitic capacitance.
