Qualcomm incorporated (20240096817). ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION simplified abstract

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ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION

Organization Name

qualcomm incorporated

Inventor(s)

Ranadeep Dutta of Del Mar CA (US)

Jonghae Kim of San Diego CA (US)

Je-Hsiung Lan of San Diego CA (US)

ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240096817 titled 'ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION

Simplified Explanation

The patent application describes techniques for on-chip electromagnetic interference (EMI) shielding in integrated circuits.

  • An integrated circuit includes a noise-sensitive device with a first metallization layer on one side, containing conductive routing layers forming a first side of an on-chip EMI shield.
  • A second metallization layer on the opposite side of the noise-sensitive device contains conductive routing layers forming a second side of the on-chip EMI shield.

Potential Applications

The technology can be applied in various electronic devices where EMI shielding is required, such as smartphones, tablets, laptops, and other portable electronic devices.

Problems Solved

1. Minimizing electromagnetic interference within integrated circuits. 2. Protecting noise-sensitive devices from external EMI sources.

Benefits

1. Improved performance and reliability of electronic devices. 2. Enhanced signal integrity within integrated circuits. 3. Reduction in EMI-related issues.

Potential Commercial Applications

Optimizing EMI shielding in consumer electronics for better product performance and reliability.

Possible Prior Art

Prior art may include traditional EMI shielding techniques using external shields or coatings to protect integrated circuits from electromagnetic interference.

Unanswered Questions

How does this technology compare to traditional EMI shielding methods?

This article does not provide a direct comparison between the new on-chip EMI shielding technique and traditional methods. It would be beneficial to understand the advantages and disadvantages of each approach.

What are the potential limitations or challenges in implementing this technology on a larger scale?

The article does not address any potential limitations or challenges that may arise when implementing on-chip EMI shielding in mass production. It would be important to consider factors such as cost, scalability, and compatibility with existing manufacturing processes.


Original Abstract Submitted

disclosed are techniques for on-chip electromagnetic interference (emi) shielding. in an aspect, an integrated circuit includes a noise-sensitive device, a first metallization layer disposed on a first side of the noise-sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (emi) shield around the first side of the noise-sensitive device, and a second metallization layer disposed on a second side of the noise-sensitive device opposite the first side of the noise-sensitive device, wherein the second metallization layer includes one or more conductive routing layers, and wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip emi shield around the second side of the noise-sensitive device.