Qualcomm incorporated (20240095542). SPLIT NEURAL NETWORK ACCELERATION ARCHITECTURE SCHEDULING AND DYNAMIC INFERENCE ROUTING simplified abstract
Contents
- 1 SPLIT NEURAL NETWORK ACCELERATION ARCHITECTURE SCHEDULING AND DYNAMIC INFERENCE ROUTING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SPLIT NEURAL NETWORK ACCELERATION ARCHITECTURE SCHEDULING AND DYNAMIC INFERENCE ROUTING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SPLIT NEURAL NETWORK ACCELERATION ARCHITECTURE SCHEDULING AND DYNAMIC INFERENCE ROUTING
Organization Name
Inventor(s)
Vijaya Kumar Kilari of Bangalore (IN)
Geoffrey Carlton Berry of Durham NC (US)
Hemanth Puranik of Bangalore (IN)
SPLIT NEURAL NETWORK ACCELERATION ARCHITECTURE SCHEDULING AND DYNAMIC INFERENCE ROUTING - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240095542 titled 'SPLIT NEURAL NETWORK ACCELERATION ARCHITECTURE SCHEDULING AND DYNAMIC INFERENCE ROUTING
Simplified Explanation
The abstract describes a method for accelerating machine learning on a computing device by splitting a neural network into sub-neural networks and hosting them in inference accelerators.
- Accessing a neural network
- Splitting the neural network into n sub-neural networks
- Hosting the n sub-neural networks in m inference accelerators
- Scheduling the n sub-neural networks in the m inference accelerators
- Executing the n sub-neural networks in the m inference accelerators
Potential Applications
This technology could be applied in various fields such as autonomous vehicles, healthcare diagnostics, natural language processing, and image recognition.
Problems Solved
This technology addresses the challenge of optimizing machine learning processes on computing devices by efficiently distributing the workload among multiple inference accelerators.
Benefits
The method allows for faster and more efficient execution of machine learning tasks, leading to improved performance and reduced processing time.
Potential Commercial Applications
- "Accelerating Machine Learning on Computing Devices: Enhancing Performance and Efficiency"
Possible Prior Art
One possible prior art could be the use of parallel processing techniques in machine learning to improve performance and speed of computations.
Unanswered Questions
How does this method compare to other techniques for accelerating machine learning tasks?
The article does not provide a comparison with other methods or technologies in the field.
What are the limitations or constraints of implementing this method in real-world applications?
The article does not address any potential challenges or limitations that may arise when implementing this method in practical scenarios.
Original Abstract Submitted
a method for accelerating machine learning on a computing device is described. the method includes accessing a neural network. the method also includes splitting the neural network into n sub-neural networks. the method further includes hosting the n sub-neural networks in m inference accelerators. the method also includes scheduling the n sub-neural networks in the m inference accelerators. the method further includes executing the n sub-neural networks in the m inference accelerators.
