PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE: abstract simplified (18336252)

• This abstract for appeared for patent application number 18336252 Titled 'PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE'

Simplified Explanation

The abstract describes a memory device that consists of multiple layers of gate electrodes and interconnects on a substrate. The device includes a first memory cell with two source/drain conductive lines and a channel layer and memory layer on the sides of these lines. A barrier structure and protective liner layers separate the conductive lines. Another barrier structure and protective liner layer are present on the opposite side of the first conductive line.

Original Abstract Submitted

A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.