Nvidia corporation (20240094291). FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS simplified abstract
Contents
- 1 FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS
Organization Name
Inventor(s)
Mahmut Yilmaz of Los Altos Hills CA (US)
Vinod Pagalone of San Jose CA (US)
Munish Aggarwal of Santa Clara CA (US)
Doochul Shin of Sunnyvale CA (US)
FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240094291 titled 'FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS
Simplified Explanation
The circuit described in the abstract is designed to improve control over asynchronous signal crossings during circuit scan tests. It includes multiple scan registers and a decoder that translates the output of the scan registers into one-hot controls for the local clock gates of scan registers in different clock domains. Programmable registers are used to enable or disable the local clock gates in the various clock domains.
- Multiple scan registers are used in the circuit.
- A decoder translates the combined output of the scan registers into one-hot controls.
- Local clock gates of scan registers in different clock domains are controlled.
- Programmable registers enable or disable the local clock gates in the different clock domains.
Potential Applications
This technology could be applied in the design and testing of integrated circuits, particularly in scenarios where asynchronous signal crossings need to be managed effectively.
Problems Solved
This circuit helps improve control over asynchronous signal crossings during circuit scan tests, which can be a challenging aspect of integrated circuit design and testing.
Benefits
The circuit provides a more efficient and reliable way to handle asynchronous signal crossings during scan tests, potentially leading to improved overall performance and reliability of integrated circuits.
Potential Commercial Applications
This technology could be valuable in the semiconductor industry for companies involved in the design and testing of integrated circuits.
Possible Prior Art
One possible prior art could be the use of programmable registers in circuit design to control clock gates in different clock domains. Another could be the use of decoders to translate outputs into control signals for various components in a circuit.
What are the specific features of the decoder used in this circuit?
The specific features of the decoder used in this circuit are not detailed in the abstract. It would be beneficial to know more about how the decoder operates and how it translates the combined output of the scan registers into one-hot controls for the local clock gates.
How does this circuit compare to existing solutions for managing asynchronous signal crossings during circuit scan tests?
The abstract does not provide a comparison of this circuit to existing solutions. It would be interesting to understand how this circuit improves upon or differs from current methods for handling asynchronous signal crossings in circuit scan tests.
Original Abstract Submitted
a circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.
