MICRON TECHNOLOGY, INC. patent applications on January 25th, 2024
Patent Applications by MICRON TECHNOLOGY, INC. on January 25th, 2024
MICRON TECHNOLOGY, INC.: 49 patent applications
MICRON TECHNOLOGY, INC. has applied for patents in the areas of G06F3/06 (16), G06F3/0604 (10), G06F3/0679 (9), H01L27/11582 (9), H01L27/11565 (8)
With keywords such as: memory, data, device, cells, source, bits, block, methods, voltage, and configured in patent application abstracts.
Patent Applications by MICRON TECHNOLOGY, INC.
Inventor(s): Tomoharu Tanaka of Yokohama (JP) for micron technology, inc., Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Dung V. Nguyen of San Jose CA (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Dave Ebsen of Minnetonka MN (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory device includes an array of memory cells and a controller configured to access the array of memory cells. the controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. the controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.
Inventor(s): Christopher Baronne of Allen TX (US) for micron technology, inc., Dean E. Walker of Allen TX (US) for micron technology, inc., Bryan Hornung of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0802
Abstract: various examples are directed to systems and methods for executing a transaction between hardware compute elements of a computing system. a first hardware compute element may send a first write request to a second hardware compute element via a network structure. the first write request may comprise first source identifier data describing the first hardware compute element and first payload data describing a processing task requested by the first hardware compute element. the network structure may store first write request state data describing the first write request. before the processing task is completed, the second hardware compute element may send a first write confirm message.
Inventor(s): Tomer Tzvi Eliash of Sunnyvale CA (US) for micron technology, inc., Yu-Chung Lien of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F11/07, G06F3/06
Abstract: methods, systems, and devices for error detection for programming single level cells of a memory system are described. the memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. the memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. the memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.
Inventor(s): Nicola Colella of Capodrise (CE) (IT) for micron technology, inc., Rakeshkumar Dayabhai Vaghasiya of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for data storage during power state transition of a memory system are described. a memory system may receive a command indicating a transition from a first power state to a second power state or a third power state. upon receiving the command, the memory system may write a first set of data to a volatile memory of the memory system. for example, the first set of data may be a snapshot or a copy of one or more elements of a second set of data. the memory system may flush the first set of data from the volatile memory to a non-volatile memory of the memory system. the memory system may transition from the first power state to the second power state or the third power state and read the snapshot from the volatile memory or the non-volatile memory upon transitioning back to the first power state.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory sub-system, such as a solid-state drive, configured to map a write stream to superblocks without the stream identifying a zone having a predetermined size in a namespace. the memory sub-system is configured to maintain, for the stream, a cursor configured to identify one of the plurality of superblocks as being reserved entirely for the stream; map, based on a superblock identified by the cursor, logical addresses of write commands in a contiguous segment of the stream to physical addresses in the superblock until the superblock is full; store data of write commands in the stream into based on mapping from logical addresses to physical addresses identified via the cursor; and allocate, for the cursor and in response to the superblock identified by the cursor being full, a free superblock available to continue mapping logical addresses to physical address.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a host system to query, during booting up of the host system, a superblock size in a connected memory sub-system. the host system can place write requests into separate streams and send the streams to the memory sub-system to store data of the write requests into separate sets of superblocks for the streams respectively. the host system can allocate, a plurality of log buffers for the streams respectively and record, into the log buffers, sequences of logical addresses as in the streams respectively. the host system can trim a stream, among the plurality of streams, by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a log buffer for the stream, causing the memory sub-system to free at least one superblock.
Inventor(s): Kumar VKH Kanteti of Sunnyvale CA (US) for micron technology, inc., Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory sub-system can determine a block granularity for an input/output (i/o) data stream received from a host system. the memory sub-system can determine that the block granularity is different than a memory block granularity of a first memory region in a first namespace of the one or more memory devices, where the first memory region is to store the i/o data stream. the memory sub-system can accumulate blocks from the i/o data stream in a second memory region in a second namespace of the one or more memory devices. responsive to a capacity of the accumulated blocks in the second memory region satisfying a threshold criterion, the memory sub-system can migrate the accumulated plurality of blocks from the second memory region to the first memory region.
Inventor(s): Yoav Weinberg of Thornhill (CA) for micron technology, inc., Nicola Pantaleo of Toronto (CA) for micron technology, inc., Leonid Minz of Beer Sheva (IL) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods of operating memory systems with input/output expanders for multi-channel status reads (and associated systems and devices) are disclosed herein. in one embodiment, a method comprises receiving, via a controller-side communication channel, a multi-channel status read command at a first interface of an input/output expander. the method further comprises, based at least in part on receiving the multi-channel status read command, (a) transmitting, via a second interface of the input/output expander, a status read command to logical units over each of two or more memory-side channels; (b) receiving, at the second interface, status read data from the logical units over each memory-side channel of the two or more memory-side channels; and (c) transmitting, via the first interface, the status read data onto the controller-side communication channel.
20240028247.EFFICIENT ERROR SIGNALING BY MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Steffen Buch of Munich (DE) for micron technology, inc., Thomas Hein of Munich (DE) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for efficient error signaling by memory are described. when executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. the memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. the memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.
Inventor(s): Murong Lang of San Jose CA (US) for micron technology, inc., Christina Papagianni of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Ting Luo of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for cross-temperature mitigation in a memory system are described. a memory system may determine a first temperature of the memory system. based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. the memory system may then determine a second temperature of the memory system after writing the set of data to the first block. based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.
Inventor(s): Emanuele Confalonieri of Segrate (IT) for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc., Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory controller can include media controllers respectively coupled to memory devices. a first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Dung V. Nguyen of San Jose CA (US) for micron technology, inc., Dave Scott Ebsen of Minnetonka MN (US) for micron technology, inc., Tomoharu Tanaka of Yokohama (JP) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: exemplary methods, apparatuses, and systems include a quick charge loss (qcl) mitigation manager for controlling writing data bits to a memory device. the qcl mitigation manager receives a first set of data bits for programming to memory. the qcl mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. the qcl mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
Inventor(s): Avinash Rajagiri of Boise ID (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Aman Gupta of Boise ID (US) for micron technology, inc., Shuji Tanaka of Kanagawa (JP) for micron technology, inc., Masashi Yoshida of Kanagawa (JP) for micron technology, inc., Shinji Sato of Kanagawa (JP) for micron technology, inc., Yingda Dong of Los Altos CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory device can include a memory array coupled with a control logic. the control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. the control logic causes a program voltage to be applied to a selected word line during the program phase. the control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. the control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Lakshmi Kalpana Vakati of San Jose CA (US) for micron technology, inc., Vivek Shivhare of Milpitas CA (US) for micron technology, inc., Dave Scott Ebsen of Minnetonka MN (US) for micron technology, inc., Sanjay Subbarao of Irvine CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and apparatuses include receiving a write command including user data. the write command is directed to a portion of memory including a first block and a second block. a buffer is allocated for executing the write command to the first block. the buffer includes multiple buffer decks and the buffer holds the user data written to the first block. user data is programmed into the first block to a threshold percentage. the threshold percentage is less than one hundred percent of the first block. a buffer deck is invalidated in response to programming the first block to the threshold percentage. the buffer deck is reallocated to the second block for programming the user data into the second block. the buffer deck holds user data written to the second block.
20240028260.MEMORY MODULE INTERFACES_simplified_abstract_(micron technology, inc.)
Inventor(s): Robert M. Walker of Raleigh NC (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F13/42, G11C7/10
Abstract: the present disclosure includes apparatuses and methods related to memory module interfaces. a memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. memory modules may thus be added or removed from a system without impacting a pcb-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. the host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.
20240028261.STACK MANAGEMENT IN MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Alex Frolikov of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory system having a stack memory, a set of media, and a controller. the controller divides the stack memory into a plurality of stacks, measures usages of the stacks in a period of time of operating on the set of media, and adjusts partitioning of the stack memory into the plurality of stacks according to the measured usages.
Inventor(s): Christopher Baronne of Allen TX (US) for micron technology, inc., Michael Keith Dugan of Richardson TX (US) for micron technology, inc., Bryan Hornung of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F9/48, G06F9/50
Abstract: various examples are directed to an arrangement comprising a first hardware compute element and a hardware balancer element. the first hardware compute element may send a first request message to a hardware balancer element. the first request message may describe a processing task. the hardware balancer element may send a second request message towards a second hardware compute element for executing the processing task and send to the first compute element a first reply message in reply to the first request message. after sending the first reply message, the hardware balancer element may receive a first completion request message indicating that the processing task is assigned and send, to the first hardware computing element, a second completion request message, the second completion request message indicating that the processing task is assigned.
20240028450.BIT AND SIGNAL LEVEL MAPPING_simplified_abstract_(micron technology, inc.)
Inventor(s): Stefan Dietrich of Türkenfeld (DE) for micron technology, inc., Martin Brox of München (DE) for micron technology, inc., Michael Dieter Richter of Ottobrunn (DE) for micron technology, inc., Thomas Hein of München (DE) for micron technology, inc., Ronny Schneider of Höhenkirchen-Siegertsbrunn (DE) for micron technology, inc., Natalija Jovanovic of München (DE) for micron technology, inc.
IPC Code(s): G06F11/10
Abstract: methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. some cyclic redundancy check (crc) calculations may generate one or more bits of crc output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more crc output bit to a physical level of the signal. the conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. for example, a modulation scheme or mapping process may be configured to map different values of crc output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/10, G11C16/04, G11C16/26, G11C16/10
Abstract: methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. a memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. the memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. the memory device may transmit the logical-to-physical table to the host device for storage at the host device. the host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.
Inventor(s): Christopher Baronne of Allen TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F13/16, G06F13/40
Abstract: various examples are directed to systems and methods for requesting an atomic operation. a first hardware compute element may send a first request via a network structure, where the first request comprises an atomic opcode indicating an atomic operation to be performed by a second hardware compute element. the network structure may provide an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element. the second hardware compute element may execute the atomic operation and send confirmation data indicating completion of the atomic operation. the network structure may provide a second bus from the second hardware compute element and the first hardware compute element. the second bus may be for providing the confirmation data from the second hardware compute element to the first hardware compute element.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F13/40, G06F13/16
Abstract: a storage product manufactured as a computer component to facilitate network storage services. the storage product has no central processing unit. the storage product has a bus connector connectable to a computer bus. an external processor connected to the computer bus can operate as a central processing unit. the storage product has a random-access memory, a network interface, a processing device, and a storage device having a storage capacity accessible via the network interface. the bus connector provides the processor with access to the random-access memory. the processing device of the storage product can identify and separate, among messages received by the network interface, first messages for processing by the external processor and second messages for processing by the storage device.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): G06F21/57
Abstract: in some aspects, the techniques described herein relate to a system including: a storage array; a controller, the controller configured to detect booting of the system; and an auto-measure circuit configured to: read a status register, the status register storing a state of data stored in the storage array, measure the data to generate a measurement, if a value stored in the status register indicates the data is compromised, compare the measurement to a golden measurement, halt booting if the measurement does not match the golden measurement, and continue booting if the measurement matches the golden measurement. further, the method can include measuring the data to generate a second measurement upon shutdown, comparing the second measurement to the value of the golden measurement register, and update the status register as negative if the second measurement does not match the value of the golden measurement register or positive otherwise.
Inventor(s): Christian M. Gyllenskog of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F21/60, H04L67/52, G06F21/62
Abstract: data can be stored in a computing device as encrypted to prevent the data from being read and/or modified without being decrypted using cryptographic information. to prevent the data from being decrypted in locations other than a secure location, the cryptographic information can be removed logically and physically from the computing device when it is determined that the computing device has left the secure location.
Inventor(s): Mark K. Hadrick of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10
Abstract: methods, apparatuses, and systems related to die-to-die communications are described. an apparatus may include a master die and a slave die communicatively coupled to each other through an internal bus. the apparatus can be configured to use an internal command and/or a data clock to coordinate the storage/write operation at the slave die instead of or in addition to a command address clock.
Inventor(s): Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/22, G11C11/4076, H03K5/156, G11C7/10
Abstract: apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. the duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. determining when to use the smaller adjustment may be based on duty cycle results. a duty cycle monitor may have an offset. a duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. the duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
Inventor(s): Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/22, G11C11/4076, H03K5/156, G11C7/10
Abstract: apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. the duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. determining when to use the smaller adjustment may be based on duty cycle results. a duty cycle monitor may have an offset. a duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. the duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
Inventor(s): Stephen W. Russell of Boise ID (US) for micron technology, inc., Lorenzo Fratin of Buccinasco (IT) for micron technology, inc., Enrico Varesi of Milano (IT) for micron technology, inc., Paolo Fantini of Vimercate (IT) for micron technology, inc.
IPC Code(s): G11C8/10, G11C8/14, H01L23/522, H10B63/00, H10N70/00
Abstract: methods, systems, and devices for word line structures for three-dimensional memory arrays are described. a memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. the word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. each word line structure may include word line members and a word line plate that is connected to each word line member. each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. to couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.
20240029778.BANK SELECTION FOR REFRESHING_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406
Abstract: in various examples, refreshing a bank can include receiving a refresh command, wherein the refresh command comprises selector bits and receiving mode register bits from the mode registers. refreshing a bank can also include refreshing a number of banks from the plurality of banks utilizing the mode register bits and the selector bits.
Inventor(s): Maksim KUZMENKA of München (DE) for micron technology, inc., Fabien FUNFROCK of Munich (DE) for micron technology, inc.
IPC Code(s): G11C11/4076, H03K3/03
Abstract: a memory device may include memory cell array a clock circuit configured to generate a plurality of clock signals for access operations associated with the memory cell array. the clock circuit may include a ring oscillator circuit that is configured to equalize phase distortions of the plurality of clock signals.
Inventor(s): JOHN F. SCHRECK of BOISE ID (US) for micron technology, inc., JASON M. JOHNSON of BOISE ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/4097, G11C29/12
Abstract: embodiments of the disclosure are drawn to apparatuses and methods for repairing multiple bit lines with a same column select value. a memory mat may be bordered by a first gap and a second gap. each gap includes sets of sense amplifiers and a redundant sense amplifier set. the sense amplifier sets are activated by an enable signal and share a column select (cs) signal in common. the redundant sense amplifier set is activated by a redundant enable signal separate from the enable signal. in some embodiments, the redundant sense amplifier sets are coupled to a redundant cs signal which is separate from the cs signal.
20240029783.SEMICONDUCTOR DEVICE HAVING BUFFER CIRCUIT_simplified_abstract_(micron technology, inc.)
Inventor(s): Yuki Miura of Sagamihara (JP) for micron technology, inc., Ken Ota of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C11/4093, G11C11/4096, G11C29/52
Abstract: disclosed herein is an apparatus that includes: first and second memory groups including a plurality of first and second memory cells, respectively; a first buffer circuit configured to receive a plurality of first data bits from the first memory group; a second buffer circuit configured to receive a plurality of second data bits from the second memory group; a first error correction circuit configured to correct at least one of the plurality of first data bits; and a second error correction circuit configured to correct at least one of the plurality of second data bits. the first error correction circuit is arranged between the first and second buffer groups of the first buffer circuit in physical layout. the second error correction circuit is arranged between the third and fourth buffer groups of the second buffer circuit in physical layout.
20240029788.DETERMINING SOFT DATA_simplified_abstract_(micron technology, inc.)
Inventor(s): Violante Moschiano of Avezzano (IT) for micron technology, inc., Andrea D'Alessandro of L'Aquila (IT) for micron technology, inc., Andrea Giovanni Xotta of Castelgomberto (IT) for micron technology, inc.
IPC Code(s): G11C11/56, G06F11/10, G11C16/34, G11C16/26, G11C29/52, H03M13/45
Abstract: the present disclosure includes apparatuses and methods for determining soft data. a number of embodiments include determining soft data associated with a data state of a memory cell. in a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.
Inventor(s): Lifang Xu of Boise ID (US) for micron technology, inc., Anna Maria Conti of Milano (IT) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc., H. Montgomery Manning of Eagle ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L27/11519, H01L27/11524, H01L27/11556, H01L27/1157, H01L27/11565, H01L27/11582
Abstract: a method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. the stack extends from a memory-array region into a stair-step region. the first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. a first layer of imageable resist is exposed to actinic radiation and developed to form a first opening there-through in the stair-step region. the developed first layer is used in a plurality of alternating etching and lateral-trimming steps that widens the first opening and forms two opposing flights of stairs in the stack in the stair-step region. a second layer of imageable resist is formed directly above the two opposing flights of stairs. the second layer is exposed to actinic radiation and developed to form a second opening there-through. the second opening exposes all of the stairs of one of the two opposing flights. the second layer is directly above all of the stairs in the other of the two opposing flights. the developed second layer is used in a plurality of alternating etching and lateral-trimming steps that widens the second opening, lengthens at least one of the two opposing flights of stairs, and extends the two opposing flights of stairs deeper into the stack. other embodiments, including structure, are disclosed.
Inventor(s): Anna Maria Conti of Milano (IT) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L27/11519, H01L27/11524, H01L27/11556, H01L27/11565, H01L27/1157, H01L27/11582
Abstract: memory circuitry comprising strings of memory cells comprises channel-material strings of memory cells extending through insulative tiers and conductive tiers in a memory-array region. the insulative and conductive tiers extend from the memory-array region into a stair-step region. a plurality of stair-step structures is in the stair-step region. the stair-step structures individually comprise two opposing flights of stairs. the stair-step structures comprise an sgd stair-step structure and non-sgd stair-step structures. at least one of the non-sgd stair-step structures has less total stairs than are in individual of multiple others of the non-sgd stair-step structures. other embodiments, including method, are disclosed.
20240029796.UNIPOLAR PROGRAMMING OF MEMORY CELLS_simplified_abstract_(micron technology, inc.)
Inventor(s): Innocenzo Tortorelli of Cernusco Sul Naviglio (IT) for micron technology, inc., Mattia Robustelli of Milano (IT) for micron technology, inc., Alessandro Sebastiani of Piacenza (IT) for micron technology, inc., Matteo Impala' of Milano (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/20, G11C16/04
Abstract: systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. a memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. the current is a set pulse or a reset pulse. the set pulse and the reset pulse have a same polarity.
20240029800.TECHNIQUES FOR THRESHOLD VOLTAGE SCANS_simplified_abstract_(micron technology, inc.)
Inventor(s): Aniello Palomba of Marigliano (Na) (IT) for micron technology, inc., Ciro Feliciano of Casandrino (Na) (IT) for micron technology, inc., Antonio Imperiale of Caserta (IT) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/26
Abstract: methods, systems, and devices for threshold voltage scans are described. a memory device may receive a configuration for scanning a memory array during a scanning procedure. the memory device may read, during the scanning procedure, one or more memory cells of the memory array using a first voltage value that is indicated by the configuration. the memory device may store, during the scanning procedure, a first value in a first counter in response to reading the one or more memory cells of the memory array. the memory device may determine whether to terminate the scanning procedure in response to one or both of determining that the first quantity of memory cells satisfies a threshold quantity of memory cells or determining that the first voltage value satisfies a threshold voltage value to be scanned.
Inventor(s): Dung Viet Nguyen of San Jose CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Zhengang Chen of San Jose CA (US) for micron technology, inc., Shantilal Rayshi Doru of San Diego CA (US) for micron technology, inc., Hope Abigail Henry of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/26
Abstract: described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. an example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. the controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.
20240029802.READ DISTURB MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhenming Zhou of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Li-Te Chang of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C11/406
Abstract: an example system can include a memory device and a processing device. the memory device can include a group of memory cells. the processing device can be coupled to the memory device. the processing device can be configured to determine a distance of a memory die from a center of a memory component. the processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.
Inventor(s): Sheyang Ning of San Jose CA (US) for micron technology, inc., Lawrence Celso Miranda of San Jose CA (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., Ting Luo of San Jose CA (US) for micron technology, inc., Luyen Vu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C29/44, G11C7/10, G11C29/12
Abstract: apparatus might include an array of memory cells and a controller for access of the array of memory cells. the controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate n determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein n is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the n determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the n determinations indicating activation of the memory cell.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Dave Scott Ebsen of Minnetonka MN (US) for micron technology, inc., Lakshmi Kalpana Vakati of San Jose CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc., Sanjay Subbarao of Irvine CA (US) for micron technology, inc., Vivek Shivhare of Milpitas CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/02
Abstract: methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. a deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. the current block is composed of multiple decks. the deck programming order is an order in which the multiple decks are programmed. the multiple decks programmed according to the determined deck programming order.
Inventor(s): Synn Nee Chow of Singapore (SG) for micron technology, inc., Robert Brian Skaggs of Kuna ID (US) for micron technology, inc., Chao Lin Lee of Singapore (SG) for micron technology, inc., Alex James Schrinsky of Boise ID (US) for micron technology, inc.
IPC Code(s): H01J37/32, H01J37/34
Abstract: methods, systems, and apparatuses for erosion rate monitoring for wafer fabrication equipment are described to support determining a real-time edge ring erosion rate for an edge ring used in manufacturing memory devices or other semiconductor devices. a manufacturing system may support a real-time edge ring erosion rate determination using force sensors, which may measure the weight of the edge ring. the controller may correlate the measured weight to a height of the edge ring. the controller may use the height to adjust a vertical placement of the edge ring, or one or more other manufacturing variables, during manufacturing operations, which may compensate for edge ring erosion and reduce or eliminate yield loss when manufacturing a memory device or other semiconductor device.
20240030058.SHALLOW TRENCH ISOLATION SPACERS_simplified_abstract_(micron technology, inc.)
Inventor(s): Chen Yang of Shaanxi (CN) for micron technology, inc.
IPC Code(s): H01L21/762
Abstract: methods, systems, and devices for shallow trench isolation spacers are described. in some examples, shallow trenches may be formed in a silicon wafer and one or more dielectric materials may be formed in the trenches. a portion of the dielectric material may subsequently be removed (e.g., etched) and a spacer material may be formed in the trenches. in some examples, portions of the spacer material may be removed (e.g., etched) and the trenches may be filled with the dielectric material. the resulting trench may include one or more spacers that isolate the dielectric material from a gate oxide or other materials formed above the silicon wafer.
Inventor(s): Youngkwon JO of Meridian ID (US) for micron technology, inc., Won Joo YUN of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: implementations described herein relate to various structures, integrated assemblies, and memory devices. in some implementations, a semiconductor package may include a substrate having a first plurality of substrate bond pads and a second plurality of substrate bond pads, and a semiconductor die having a first plurality of die bond pads and a second plurality of die bond pads. each die bond pad, included in the first plurality of die bond pads, may be connected to a corresponding substrate bond pad, included in the first plurality of substrate bond pads, using bump bonding, and each die bond pad, included in the second plurality of die bond pads, may be connected to a corresponding substrate bond pad, included in the second plurality of substrate bond pads, using wire bonding.
20240030219.LOGIC GATES_simplified_abstract_(micron technology, inc.)
Inventor(s): Wenjun Li of Meridian ID (US) for micron technology, inc., Seong-Dong Kim of Boise ID (US) for micron technology, inc., Anda Mocuta of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/088, H03K19/20
Abstract: embodiment herein relate to logic gates. an example of a logic gate includes a semiconductor material, source regions having a first width, drain regions having a second width that is different than the first width, transistor gates, and electrical contacts coupled to the source regions and the drain regions.
Inventor(s): Collin Howder of Boise ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/08, H01L27/1157, H01L27/11565, H01L29/417
Abstract: electronic devices comprising a source stack comprising one or more conductive materials, a source implant region within a top portion of the source stack, a source contact adjacent to the source stack, sidewalls of the source contact vertically adjacent to the source implant region, a doped semiconductive material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped semiconductive material, and pillars extending through the tiers, the doped semiconductive material, and the source contact and into the source stack. additional electronic devices are also disclosed, as are related methods and electronic systems.
Inventor(s): Scott D. Schellhammer of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L33/02, H01L33/24, H01L33/00, H01L33/06
Abstract: semiconductor lighting devices and associated methods of manufacturing are disclosed herein. in one embodiment, a semiconductor lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. the semiconductor lighting device also includes an indentation extending from the second semiconductor material toward the active region and the first semiconductor material and an insulating material in the indentation of the solid state lighting structure.
20240030940.COMMAND ADDRESS FAULT DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Aaron P. BOEHM of Boise ID (US) for micron technology, inc., Melissa I. URIBE of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): H03M13/11, H03M13/09, G11C8/06
Abstract: implementations described herein relate to command address fault detection. a memory device may receive, from a host device via a command address (ca) bus, a plurality of bits associated with a command signal or an address signal. the ca bus may be configured for communicating command signals and address signals between the memory device and the host device. the memory device may generate one or more parity bits based on the plurality of bits. the one or more parity bits may be generated using a parity generation process that is common to the memory device and the host device. the memory device may transmit, to the host device, the one or more parity bits.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L27/11582, H01L27/11556, H01L27/11519, H01L27/11565
Abstract: an electronic device comprising a source stack comprising one or more conductive materials, and an oxide fill region within an upper portion of the source stack. a source contact is adjacent to the source stack and the oxide fill region, and a doped semiconductive material is adjacent to the source contact. tiers of alternating conductive materials and dielectric materials are adjacent to the doped semiconductive material, and pillars extend through the tiers, the doped semiconductive material, and the source contact and into the source stack. additional electronic devices are also disclosed, as are related methods and electronic systems.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/11582, H01L27/11543, H01L21/28
Abstract: electronic devices comprising a source stack comprising one or more conductive materials, a source contact adjacent to the source stack, tiers of alternating conductive materials and insulative materials adjacent to the source contact, pillars extending through the tiers and the source contact and into the source stack, a slit structure extending through the tiers and the source contact, and an implant structure extending within the slit structure and into the source stack. related methods and systems are also disclosed.
MICRON TECHNOLOGY, INC. patent applications on January 25th, 2024
- MICRON TECHNOLOGY, INC.
- G06F3/06
- Micron technology, inc.
- G06F12/0802
- G06F11/07
- G06F13/42
- G11C7/10
- G06F9/48
- G06F9/50
- G06F11/10
- G06F12/10
- G11C16/04
- G11C16/26
- G11C16/10
- G06F13/16
- G06F13/40
- G06F21/57
- G06F21/60
- H04L67/52
- G06F21/62
- G11C7/22
- G11C11/4076
- H03K5/156
- G11C8/10
- G11C8/14
- H01L23/522
- H10B63/00
- H10N70/00
- G11C11/406
- H03K3/03
- G11C11/4091
- G11C11/4097
- G11C29/12
- G11C11/4093
- G11C11/4096
- G11C29/52
- G11C11/56
- G11C16/34
- H03M13/45
- H01L27/11519
- H01L27/11524
- H01L27/11556
- H01L27/1157
- H01L27/11565
- H01L27/11582
- G11C16/20
- G11C29/42
- G11C29/44
- G11C29/02
- H01J37/32
- H01J37/34
- H01L21/762
- H01L23/00
- H01L27/088
- H03K19/20
- H01L29/08
- H01L29/417
- H01L33/02
- H01L33/24
- H01L33/00
- H01L33/06
- H03M13/11
- H03M13/09
- G11C8/06
- H01L27/11543
- H01L21/28
- G06F3/0604
- G06F3/0679
