MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY: abstract simplified (17715964)

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  • This abstract for appeared for patent application number 17715964 Titled 'MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY'

Simplified Explanation

This abstract describes a memory array and its components, as well as an operation method. The memory array consists of memory cells, floating gate transistors, bit lines, and word lines. Each memory cell includes a capacitor and an electrically programmable non-volatile memory (NVM) connected in series, as well as a write transistor connected to a common node of the capacitor and the NVM. The floating gate transistors are connected to the capacitors of a column of memory cells, while the bit lines are connected to the NVMs of a row of memory cells. The word lines are connected to the gate terminals of the write transistors in a row of memory cells.


Original Abstract Submitted

A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.

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