Kioxia corporation (20240099027). NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD simplified abstract

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD

Organization Name

kioxia corporation

Inventor(s)

Kensuke Takahashi of Yokkaichi Mie (JP)

Daisaburo Takashima of Yokohama Kanagawa (JP)

Naoki Kai of Kuwana Mie (JP)

Yasumi Ishimoto of Yokkaichi Mie (JP)

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240099027 titled 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD

Simplified Explanation

The patent application describes a cell block structure for memory cells, including memory cells, select transistors, and resistance change elements. Here are some key points to explain the innovation:

• Memory cells are connected in parallel between a local source line and a local bit line.
• Each memory cell includes a cell transistor and a resistance change element.
• The select transistor is connected between the local bit line and a bit line.
• The resistance change element is connected to the cell transistor in series between the local source line and the local bit line.
• The cell block is configured as a columnar structure with conductive films functioning as word lines.
• The select transistor and the local bit line are connected at a contact portion formed of a material different from the local bit line material.

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1. 1. 1. Potential Applications

• Non-volatile memory devices
• Solid-state drives
• Wearable technology

1. 1. 1. Problems Solved

• Increased memory density
• Improved data retention
• Enhanced memory cell performance

1. 1. 1. Benefits

• Faster data access
• Lower power consumption
• Higher reliability

1. 1. 1. Potential Commercial Applications
         1. Optimizing Memory Cell Structures for Improved Performance

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1. 1. 1. Possible Prior Art

There may be prior art related to memory cell structures and non-volatile memory devices that could be relevant to this patent application.

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1. 1. 1. 1. Unanswered Questions

1. 1. 1. How does this innovation compare to existing memory cell structures in terms of performance and reliability?

The article does not provide a direct comparison with existing memory cell structures in terms of performance and reliability. Further research or testing may be needed to evaluate the advantages of this innovation over current technologies.

1. 1. 1. What are the potential manufacturing challenges associated with implementing this cell block structure in memory devices?

The article does not address potential manufacturing challenges associated with implementing this cell block structure in memory devices. It would be important to consider factors such as cost, scalability, and compatibility with existing manufacturing processes when developing this technology for commercial use.

Original Abstract Submitted

according to one embodiment, a cell block includes memory cells and select transistors. the memory cells correspond are connected in parallel between a local source line and a local bit line. the select transistor is connected between the local bit line and a bit line. the memory cell includes a cell transistor and a resistance change element. a gate of the cell transistor is connected to a word line. the resistance change element is connected to the cell transistor in series between the local source line and the local bit line. each cell block is configured as a columnar structure penetrating a plurality of conductive films functioning as word lines. the select transistor and the local bit line are connected at a contact portion formed of a material different from a material of the local bit line.