Kioxia corporation (20240097687). SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT SYSTEM simplified abstract
Contents
- 1 SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT SYSTEM
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT SYSTEM - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT SYSTEM
Organization Name
Inventor(s)
Kiyohito Sato of Kawasaki Kanagawa (JP)
SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240097687 titled 'SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT SYSTEM
Simplified Explanation
The patent application describes a semiconductor integrated circuit that includes multiple oscillation circuits and a detection circuit to synchronize clock signals and maintain a frequency-locked state. A control circuit adjusts the control signal to minimize frequency differences between clock signals.
- First oscillation circuit receives a clock signal and outputs a synchronized clock signal.
- Second oscillation circuit generates a clock signal based on a control signal.
- Detection circuit identifies frequency differences between clock signals.
- Determination circuit checks for frequency-locked state between clock signals.
- Control circuit adjusts control signal to minimize frequency differences.
Potential Applications
This technology can be applied in various electronic devices requiring precise clock signal synchronization, such as communication systems, data processing units, and timing circuits.
Problems Solved
1. Ensures accurate synchronization of clock signals. 2. Maintains a stable frequency-locked state between clock signals.
Benefits
1. Improved performance and reliability of electronic devices. 2. Enhanced efficiency in data processing and communication systems.
Potential Commercial Applications
Optimizing Clock Signal Synchronization in Semiconductor Integrated Circuits
Possible Prior Art
There may be prior art related to clock signal synchronization and frequency control in semiconductor integrated circuits, but specific examples are not provided in this context.
Unanswered Questions
How does this technology compare to existing clock signal synchronization methods in terms of efficiency and accuracy?
This article does not provide a direct comparison with existing methods, leaving the reader to speculate on the potential advantages of this innovation.
What are the potential limitations or challenges in implementing this technology on a larger scale in complex integrated circuits?
The article does not address the scalability or practical challenges of integrating this technology into more complex semiconductor devices, leaving room for further exploration and analysis.
Original Abstract Submitted
in a semiconductor integrated circuit, a first oscillation circuit receives a first clock signal and outputs a second clock signal synchronized with the first clock signal in frequency and phase. a second oscillation circuit receives a control signal and outputs a third clock signal having a frequency corresponding to the received control signal. a detection circuit detects a frequency difference between the second clock signal and the third clock signal. a determination circuit determines whether a frequency locked state is established between the first clock signal and the second clock signal. a control circuit varies the control signal, such that the frequency difference decreases while the frequency locked state has not been established and increases after the frequency locked state is established.
