Kioxia corporation (20240096429). SEMICONDUCTOR STORAGE DEVICE simplified abstract

SEMICONDUCTOR STORAGE DEVICE

Organization Name

kioxia corporation

Inventor(s)

Shingo Nakazawa of Kamakura Kanagawa (JP)

Yuki Inuzuka of Yokohama Kanagawa (JP)

SEMICONDUCTOR STORAGE DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240096429 titled 'SEMICONDUCTOR STORAGE DEVICE

Simplified Explanation

The semiconductor storage device described in the patent application includes a complex structure with multiple word lines, select gate lines, memory cells, select transistors, and a logic control circuit. The device is designed to perform read operations on memory cells by independently controlling select gate lines to isolate the memory cell being read from other memory cells.

• The semiconductor storage device includes a first memory pillar with a first memory cell connected to the first word line.
• The device also includes a logic control circuit that reads threshold voltages of memory cells using select transistors connected to select gate lines.
• During a read operation, the logic control circuit turns off select transistors connected to memory cells other than the one being read to prevent interference.

Potential Applications

The technology described in this patent application could be applied in:

• Solid-state drives
• Flash memory devices
• Embedded systems

Problems Solved

This technology addresses issues related to:

• Accurate reading of threshold voltages in memory cells
• Efficient control of select gate lines during read operations

Benefits

The benefits of this technology include:

• Improved reliability in reading data from memory cells
• Enhanced performance in semiconductor storage devices

Potential Commercial Applications

The potential commercial applications of this technology could be seen in:

• Consumer electronics
• Data storage solutions
• Automotive electronics

Possible Prior Art

One possible prior art for this technology could be the use of similar select gate line control mechanisms in other semiconductor storage devices.

How does this technology impact the speed of read operations in semiconductor storage devices?

This technology can potentially improve the speed of read operations by efficiently controlling select gate lines and isolating the memory cell being read.

What are the implications of independently controlling select gate lines on the power consumption of the semiconductor storage device?

Independently controlling select gate lines during read operations may have implications on power consumption, potentially leading to more efficient energy usage in the device.

Original Abstract Submitted

a semiconductor storage device includes a first word line, a second word line, a first select gate line, a second select gate line, a third select gate line, a fourth select gate line, a first memory pillar including a first memory cell connected to the first word line, a first select transistor connected to the first select gate line, a second memory cell connected to the second word line, and a second select transistor connected to the second select gate line, and a logic control circuit configured to perform a read operation to read threshold voltages of the first and second memory cells, respectively. the logic control circuit independently controls the first to fourth select gate lines during the read operation to turn the select transistors electrically connected to memory cells other than the memory cell to be read to off state.