Kioxia corporation (20240096422). STORAGE DEVICE simplified abstract
Contents
STORAGE DEVICE
Organization Name
Inventor(s)
Hiroaki Kosako of Yokkaichi Mie (JP)
Kota Nishikawa of Zama Kanagawa (JP)
Kenrou Kikuchi of Fujisawa Kanagawa (JP)
STORAGE DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240096422 titled 'STORAGE DEVICE
Simplified Explanation
The patent application describes a memory cell structure with select transistors and memory cell transistors connected in series, along with word lines connected to the memory cell transistors. Different voltages are applied to the word lines during different periods to control the operation of the memory cell structure.
- Select transistors and memory cell transistors are connected in series.
- Word lines are connected to the memory cell transistors.
- Different voltages are applied to the word lines during different periods.
Potential Applications
The technology described in the patent application could be applied in various memory devices, such as non-volatile memory, flash memory, and other types of semiconductor memory.
Problems Solved
This technology helps in improving the performance and efficiency of memory devices by providing a more controlled and efficient way of accessing and storing data.
Benefits
The benefits of this technology include faster data access, lower power consumption, and increased reliability of memory devices.
Potential Commercial Applications
The technology could be used in a wide range of commercial applications, including consumer electronics, data storage devices, and computer systems.
Possible Prior Art
One possible prior art for this technology could be the use of select transistors and word lines in memory cell structures to control data access and storage.
Unanswered Questions
How does this technology compare to existing memory cell structures in terms of speed and efficiency?
This article does not provide a direct comparison between this technology and existing memory cell structures in terms of speed and efficiency. Further research and testing would be needed to determine the exact performance differences.
What are the potential challenges in implementing this technology on a larger scale for commercial production?
The article does not address the potential challenges in implementing this technology on a larger scale for commercial production. Factors such as manufacturing costs, scalability, and compatibility with existing systems could pose challenges that need to be explored further.
Original Abstract Submitted
a first select transistor is connected to a first wiring. a first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. a first word line is connected to the first memory cell transistor. a second word line is connected to the second memory cell transistor. during a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. during a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line. during a third period in which the third voltage is applied to the first wiring, the fourth voltage is applied to the first word line, and the second voltage is applied to the second word line.
