Kioxia Corporation patent applications published on September 21st, 2023

POLISHING APPARATUS AND POLISHING METHOD (17929128)

Abstract

A polishing apparatus is configured to polish a peripheral edge of an object. The apparatus includes: a stage having a mounting surface to mount the object; a polishing head configured to press a polishing surface against the peripheral edge and polish the peripheral edge; a first inlet configured to supply liquid to the polishing surface; and a protector having a first surface extending along a first direction intersecting with the mounting surface, the first surface having an opening between the stage and the polishing head in a second direction intersecting with the first direction.

Inventor

Takeshi KIKUCHI

SEMICONDUCTOR MANUFACTURING DEVICE (17874636)

Abstract

A semiconductor manufacturing device includes: a turntable configured to be rotatable and having a first surface; a polishing pad provided on the first surface; a first support portion configured to rotatably hold the turntable; a top ring having a second surface and including a suction mechanism that holds an object to be processed on the second surface; a second support portion configured to rotatably hold the top ring; a first member to come into contact with the turntable or top ring; a second member to come into contact with the polishing pad or suction mechanism and with the turntable or top ring via the first member; and a first AE sensor to come into contact with the second member.

Inventor

Yasuhide OKADA

FILM FORMING METHOD AND APPARATUS (17943695)

Abstract

According to one embodiment, a film forming method includes alternately performing a first process including at least two times of a first sequence and a second process including at least one time of a second sequence. The first sequence includes supplying a film forming gas into a film forming chamber, supplying a first purge gas into the film forming chamber, supplying a first reduction gas into the film forming chamber, and supplying a second purge gas into the film forming chamber, in order, and the second sequence includes supplying a second reduction gas into the film forming chamber, and supplying a third purge gas into the film forming chamber, in order.

Inventor

Shigeru KINOSHITA

SEMICONDUCTOR DEVICE AND TEST METHOD OF SEMICONDUCTOR DEVICE (17898102)

Abstract

A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current.

Inventor

Takuya KUSAKA

MEMORY TESTER AND TEST METHOD THAT USES MEMORY TESTER (17941439)

Abstract

A memory tester of the present embodiment includes a first memory, a second memory, an arithmetic circuit, and a determination circuit. The first memory is configured to store scan input data and expected value data, the scan input data including a don't care bit, the expected value data being obtained by converting the don't care bit into a first predetermined value. The second memory is configured to store scan output data and mask data obtained by converting a value of the scan input data other than the don't care bit into a second predetermined value. The arithmetic circuit is configured to perform an exclusive or operation between the expected value data and the scan output data. The determination circuit is configured to determine whether the don't care bit of an arithmetic result from the arithmetic circuit is passed or failed by using the mask data.

Inventor

Kenji YASUI

TEMPLATE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE (17842615)

Abstract

A template according to the present embodiment includes a substrate, a light transmissive film, and a plurality of convex parts. The substrate has a first surface. The light transmissive film is provided on the first surface, has a second surface on a side opposite to the substrate, and has a composition different from the composition of the substrate. The plurality of convex parts are provided on the second surface and have different heights.

Inventor

Takeharu MOTOKAWA

MEASURING DEVICE AND MEASURING METHOD (17894783)

Abstract

According to one embodiment, a measuring device includes a support body, a first light source, a second light source, a first sensor, and a second sensor. The support body is configured to support an end portion of a measurement target. The first light source is disposed on a front surface side of the support body. The second light source is disposed on a rear surface side of the support body. An optical axis of the second light source coincides with an optical axis of the first light source. The first sensor is configured to acquire an image of a mark in the measurement target in accordance with light from the first light source. The second sensor is configured to acquire an image of the mark in the measurement target in accordance with light from the second light source.

Inventor

Masakazu HAMASAKI

MEMORY SYSTEM (17898370)

Abstract

A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

Inventor

Kenta SHIBASAKI

SEMICONDUCTOR MEMORY DEVICE (17899974)

Abstract

A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

Inventor

Rieko FUNATSUKI

INFORMATION PROCESSING APPARATUS (17939150)

Abstract

According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.

Inventor

Koichi NAGAI

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY (17941388)

Abstract

According to one embodiment, a controller of a memory system writes, in response to receiving from the host a write command specifying a logical address, data received from the host to a first write destination block. The controller manages a first list and first storage location information, the first list including a plurality of logical addresses corresponding respectively to write-uncompleted data, and the first storage location information indicating a storage location at a beginning of a write-uncompleted region in the first write destination block. In a case where a power loss has occurred without notice from the host, the controller writes the first list and the first storage location information to the nonvolatile memory using power from a capacitor.

Inventor

Shinichi KANNO

STORAGE DEVICE (17900417)

Abstract

According to one embodiment, a storage device includes a first storage region assigned to a first user and a second storage region assigned to a second user. A first controller is capable of providing a data protection function to the first and second storage regions, and a second controller is capable of providing the data protection function to the second storage region. The first controller stores a table with information about the data protection function. The second controller can refer to the table. The first controller has a authority to execute a user authentication for the first storage region and the second storage region to determine whether the data protection function can be provided for the first or second storage regions.

Inventor

Kenichi NUMATA

MEMORY SYSTEM AND METHOD (17806822)

Abstract

According to one embodiment, a memory system includes first, second, and third controllers. The first/second controller sets a first/second link to an operating or low power consumption state. The third controller sends a busy signal to the first and second controllers when transfer of a packet via the first or second link is predicted. When the first link is in the low power consumption state and a packet has not been received via the first link, the first link is maintained in the low power consumption state by disabling the busy signal. When the first link is in the operating state and a packet has not been received via the first link, the first link is transitioned to the low power consumption state upon absence of packets transferred via the first link for a first period of time, by disabling the busy signal.

Inventor

Takuya SEKINE

MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM (17899547)

Abstract

A memory system connectable to an external device that can supply power thereto, includes a non-volatile memory that stores data indicating a plurality of operation modes in association with different power consumption values, and a controller configured to, upon receipt of a first command indicating a first value of the power from the external device, determine a first ratio of execution times of the operation modes, and control the non-volatile memory using the operation modes according to the determined first ratio.

Inventor

Takuya ONODERA

SEMICONDUCTOR MEMORY DEVICE (17931265)

Abstract

According to one embodiment, a semiconductor memory device includes memory cells and a control circuit configured to control an erase operation on the memory cells. The control circuit sequentially executes, in the erase operation, a first erase process, a first erase verify process, a second erase process, and a second erase verify process on the memory cells, acquires, in the first erase verify process, first memory cells having a threshold voltage equal to or lower than a first verify voltage, from among the memory cells, acquires, in the second erase verify process, the number of second memory cells having a threshold voltage higher than the first verify voltage, from among the first memory cells, and determines whether the number of the second memory cells is larger than a first value or not.

Inventor

Keita KIMURA

MEMORY SYSTEM (17939848)

Abstract

A memory system includes a non-volatile memory and a memory controller configured to receive a command including an access target in the non-volatile memory and setting information from an external device and configured to control a writing operation or a reading operation to the access target. The memory controller has a condition setting circuit. The condition setting circuit is capable of performing the writing operation or the reading operation under a plurality of different conditions. The memory controller performs the writing operation or the reading operation under one of the plurality of different conditions selected by the condition setting circuit in accordance with the setting information.

Inventor

Kosuke HATSUDA

MEMORY SYSTEM AND CONTROL METHOD (17898394)

Abstract

A memory system includes a volatile memory, a nonvolatile memory, and a controller. The controller is configured to set a block group of the nonvolatile memory to be in a writable state and generate in the volatile memory a list associated with the block group. The controller is configured to, with respect to a write command, add an entry to the list, which includes a first address of a host and a second address of the volatile memory, obtain the write data from the first address of the host and store the write data in the second address of the volatile memory, write the write data stored at the second address of the volatile memory into the block group, and upon the block group being fully written, set the block group to be in a non-writable state and dissociate the list from the block group.

Inventor

Yuki SASAKI

MEMORY SYSTEM (17839896)

Abstract

A memory system of an embodiment includes a memory, a controller configured to control the memory, and a first board on which the memory and the controller are mounted. The memory system further includes a module component including at least one capacitor, a second board, and a wiring member, each of the at least one capacitor including a lead, the at least one capacitor being mounted on the second board, the wiring member being electrically connected to the lead of the at least one capacitor and extending from the second board. The first board and the module component are connected to each other via the wiring member.

Inventor

Fuminori KIMURA

MEMORY SYSTEM AND MEMORY CONTROL METHOD (17887873)

Abstract

A memory controller determines the number of pieces of correction information of an a-th correction information for each of M component codes according to a value based on the number of component codes, and determines a correction information address which is an address on a correction information memory of the a-th correction information based on the number of pieces of correction information. The memory controller calculates an a-th soft-input value for an a-th component code, inputting the a-th soft-input value to execute decoding processing of the a-th component code, calculates a decoded word of the a-th component code, a-th correction information, and a-th reliability information, stores the a-th correction information and b-th correction information indicating a b-th corrected location (1≤b≤nj) in a j-th dimension (j≠i, 1≤j≤N) in the correction information address of the correction information memory, stores a-th reliability information in a reliability information memory, and outputs an output decoded word calculated from the read information and the reliability information of each component code.

Inventor

Takahiro KUBOTA

MEMORY SYSTEM AND METHOD (17939745)

Abstract

A memory system includes a memory controller and a first memory. The memory controller writes a plurality of first data segments of user data and metadata to a plurality of first segment regions of the first memory according to a first order. In response to a read request from a host, the memory controller individually identifies a plurality of second segment regions to which a plurality of second data segments corresponding to requested user data has been written. The memory controller determines whether or not to perform a prefetch operation according to a second order and a third order. The second order is an order of reading the second data segments from the second segment regions. The third order corresponds to the first order excluding the order of write destinations of the metadata.

Inventor

Haruka MORI

MEMORY SYSTEM AND CONTROLLING METHOD (17943972)

Abstract

According to one embodiment, a controller writes first data into a first storage area in accordance with a first write command from a host. The controller identifies a logical address mapped to the written first data. The controller writes internal data that is read from a second storage area into a first location of the first storage area. The controller associates the first storage location with the logical address. The controller reads the internal data from the first storage location in response to receiving, from the host, a read command that designates the logical address. The controller transmits, to the host, the internal data read from the first storage location.

Inventor

Yasuyuki IWAKI

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY AND FOR REDUCING A BUFFER SIZE (18301694)

Abstract

According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.

Inventor

Shinichi KANNO

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY (18322104)

Abstract

According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.

Inventor

Shinichi KANNO

MEMORY SYSTEM AND CONTROL METHOD (17898390)

Abstract

A memory system includes a nonvolatile memory including memory dies, and a controller. The controller is configured to create a first virtual storage with a first part of the memory dies and a second virtual storage with a second part of the memory dies, and create a redundant logical domain spanning one or more memory dies corresponding to the first virtual storage and one or more memory dies corresponding to the second virtual storage. The memory controller is configured to, in response to a write command, store write data corresponding to the write command in a first region of the first virtual storage and in a second region of the second virtual storage, and return to the host a response including a first physical address of the first region and a second physical address of the second region.

Inventor

Hideki YOSHIDA

MEMORY SYSTEM (18324226)

Abstract

According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

Inventor

Kengo KUROSE

INFORMATION PROCESSING SYSTEM AND MEMORY SYSTEM (17807806)

Abstract

According to one embodiment, an information processing system includes a memory system including a non-volatile memory, and a host device including a host memory and a processor executing software for accessing data stored in the non-volatile memory. The processor is configured to: allocate a cache area in the host memory to cache data stored in the non-volatile memory; when the software is executed, perform a tag lookup of the cache area, and in a case where a cache hit has occurred upon the lookup, access the cache area without accessing the non-volatile memory; and refill the data stored in the non-volatile memory into the cache area at a second frequency lower than a first frequency at which a cache miss occurs.

Inventor

Tomoya Suzuki

MEMORY SYSTEM AND METHOD (17898307)

Abstract

A memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory based on an address conversion table. The controller is configured to generate first address mapping information indicating a first logical address range and a first physical address range, and then second address mapping information indicating a second logical address range and a second physical address range, determine whether the first and second logical address ranges are continuous and the first and second physical address ranges are continuous, upon determining non-continuity of the logical or physical address ranges, update the address conversion table based on the first address mapping information, and upon determining continuity of the logical and physical address ranges, generate integrated address mapping information using the first and second address mapping information and update the address conversion table based on the integrated address mapping information.

Inventor

Takahiro KURITA

MEMORY DEVICE AND METHOD OF MANUFACTURING MEMORY DEVICE (17894795)

Abstract

According to one embodiment, a device includes a memory cell array that includes a plurality of memory cells connected to a plurality of pieces of gate wiring, and a test control circuit that includes a plurality of control units connected to the plurality of pieces of gate wiring. The control units each includes a transistor that includes a gate connected to a first node, one end connected to the corresponding gate wiring and another end connected to a second node, and a load unit connected between the first node and the second node. When the gate wiring is being discharged, the transistor is turned on. The gate wiring is connected to the second node via the transistor in an on state. After the gate wiring is discharged, the load unit discharges the first node.

Inventor

Kazuhiro NOJIMA

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE (17897710)

Abstract

A semiconductor memory device includes a first wiring, a second wiring, a columnar insulating portion, and a first insulating layer. The first insulating layer includes a first edge. When it is assumed that a position closest to the columnar insulating portion on the first edge is a first position, a position of the first insulating layer, which is different from the first edge and is closest to the columnar insulating portion, is a second position, a virtual line along the first edge is a first virtual line, and a virtual line connecting the first position and the second position is a second virtual line, a crossing angle between the first virtual line and the second virtual line as seen from an inside of the first insulating layer is 90 degrees or more.

Inventor

Yusuke MORI

SEMICONDUCTOR MEMORY DEVICE (17896907)

Abstract

A semiconductor memory device includes a memory cell array, a storing unit that stores data read out from the memory cell array in storage circuits, an output circuit, and a control circuit. In response to a read request, the control circuit adjusts the value of a read pointer of the storing unit, controls the storing unit to sequentially output to the output circuit first and second data stored in first and second storage circuits of the storing unit, respectively, the read pointer having a first value that references the first storage circuit when the first data is output, and a second value that references the second storage circuit when the second data is output, and controls the output circuit to transmit the first and second data to the memory controller as dummy data, and thereafter to transmit at least third data to the memory controller as read data.

Inventor

Shintaro HAYASHI

SEMICONDUCTOR DEVICE (17944725)

Abstract

A semiconductor device according to an embodiment includes first to fifth interconnects, first to third memory cells, and a control circuit. The control circuit is configured to execute machine learning. Each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element. In the machine learning, the control circuit is configured to: execute a write operation using a common write voltage to each of the second memory cells; and after the write operation, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.

Inventor

Kensuke OTA

MEMORY DEVICE (17843084)

Abstract

According to one embodiment, a memory device includes: a first memory cell; a second memory cell; a first circuit configured to supply a write current to the first memory cell and the second memory cell; a first wiring coupled to the first circuit; a first electrode configured to electrically couple the first memory cell to the first wiring; and a second electrode configured to electrically couple the second memory cell to the first wiring. A length of the first wiring from the first circuit to the first electrode is smaller than a length of the first wiring from the first circuit to the second electrode. A resistance value of the first electrode is higher than a second resistance value of the second electrode.

Inventor

Kuniaki SUGIURA

MEMORY SYSTEM (17896950)

Abstract

A memory system includes first and second memory cells, and a controller configured to write data having a first value in the first memory cells and data having a second value in the second memory cells, determine a first voltage by executing a tracking process, and read data from the memory cells using the first voltage. In the tracking process, the controller performs a plurality of read operations to determine a first distribution of the memory cells, estimate a second distribution of the first memory cells based on the first distribution, calculate a third distribution of the second memory cells based on a difference between the first distribution and the second distribution, and determine a voltage that is within the third voltage as the first voltage based on the second distribution and the third distribution.

Inventor

Takashi NAKAGAWA

MEMORY SYSTEM AND READ METHOD (17899293)

Abstract

According to one embodiment, a memory system includes a memory including nonvolatile memory cells, and a controller configured to set read voltages for reading data stored in the nonvolatile memory cells. The controller stores first shift patterns relating to a plurality of read voltages, first index information associating to a first shift pattern with each of a plurality of memory cell groups, second shift patterns relating to differences between read voltages and read voltages set according to a first shift pattern, and second index information associating a second shift pattern with each memory cell group. The controller generates read voltages of a target memory cell group based on the first shift pattern voltages and the second shift pattern voltages.

Inventor

Katsuyuki SHIMADA

MEMORY DEVICE (17901459)

Abstract

A memory device includes a first memory cell and a second memory cell each corresponding to a first column address, a first sense amplifier unit, a first bit line connected between the first memory cell and the first sense amplifier unit, and a second bit line connected between the second memory cell and the first sense amplifier unit.

Inventor

Hiroshi MAEJIMA

MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM (17939180)

Abstract

According to one embodiment, a controller configured to manage second test information including status information indicating that a test related to a write operation and a read operation on a second storage area has not been executed. In response to receiving a command for acquiring information related to the second storage area from a host, the controller transmits the second test information to the host. When execution of the test on the second storage area is requested by the host, the controller executes the test related to the write operation and the read operation on the second storage area, and updates the status information of the second test information.

Inventor

Masayoshi SATO

MEMORY SYSTEM AND METHOD (17896887)

Abstract

A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.

Inventor

Motoki SHIMIZU

SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD (17931230)

Abstract

A semiconductor manufacturing apparatus of embodiments includes: a chamber including a top plate and a sidewall; a holder provided in the chamber holding a substrate; a first high frequency power supply applying high frequency power to the holder or the top plate; a second high frequency power supply applying high frequency power to the holder; a third high frequency power supply applying high frequency power to the top plate; a gas supply pipe supplying a gas to the chamber; and a gas discharge pipe discharging a gas from the chamber.

Inventor

Yusuke KASAHARA

PLASMA TREATMENT APPARATUS AND PLASMA TREATMENT METHOD (17898168)

Abstract

According to one embodiment, a plasma treatment apparatus includes a substrate holder that holds a semiconductor substrate, a gas supply unit that supplies a mixed gas to a gas supply space formed between the semiconductor substrate and the substrate holder, a flow rate adjustment unit that adjusts a flow rate of different gases in the mixed gas, and a flow rate control unit. The mixed gas contains, for example, helium and argon, and the flow rate control that controls the flow rate adjustment unit to change the relative flow rates of helium and argon, or the like, to control a temperature of the substrate.

Inventor

Yusuke KONDO

PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND PATTERN FORMING APPARATUS (17900250)

Abstract

According to one embodiment, a pattern forming method includes forming a first resin pattern on a substrate with a first resin. The first resin pattern includes a first transfer pattern and a first mark. A second resin is dispensed to cover the first mark of the first resin pattern. A first pattern is formed including the first transfer pattern and the second resin covering the first mark. The first pattern is then transferred to a first process film on the substrate.

Inventor

Satoshi MITSUGI

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND PATTERNING METHOD (17891335)

Abstract

A method for manufacturing a semiconductor device is disclosed. The method includes forming a mask layer containing a first metal and a first halogen on a film to be processed. The method includes patterning the mask layer. The method includes performing a treatment on the mask layer to decrease the concentration of the first halogen. The method includes processing the film using the treated mask layer as a mask.

Inventor

Masayuki Kitamura

SUBSTRATE PROCESSING APPARATUS (17929923)

Abstract

A substrate processing apparatus of an embodiment includes: a processing tank that stores a processing solution and houses a plurality of substrates that are to be processed with the processing solution, with the substrates being arranged in a predetermined direction; an inner wall provided in the processing tank to cover at least a partial portion of a substrate surface located at one end in terms of the arrangement direction of the substrates and at least partial portions of side surfaces, of the substrates, that line up along the arrangement direction, with a space where the processing solution flows being present between the inner wall and a bottom surface of the processing tank; and a processing solution nozzle provided at a position that is in the processing tank and outside the inner wall and opening in a manner to cause an upward flow to be formed inside the inner wall.

Inventor

Shusaku MATSUMOTO

TEMPERATURE MEASUREMENT METHOD, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE (17930541)

Abstract

A temperature measurement method according to one embodiment includes a step of applying measurement light having a predetermined wavelength to a reflective film formed on a first surface of a substrate. Furthermore, the temperature measurement method includes a step of receiving, with an optical member, reflected light generated by the measurement light being reflected by the reflective film. Furthermore, the temperature measurement method includes a step of calculating the temperature of the substrate based on a reflectance based on the ratio between the intensity of the measurement light and the intensity of the reflected light.

Inventor

Naoki KOSAKA

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE (17930278)

Abstract

A semiconductor device includes a substrate , a first insulating film  provided above the substrate , a second insulating film  disposed between the substrate  and the first insulating film , a first metal pad  provided in the first insulating film , and a second metal pad  provided in the second insulating film , the second metal pad  being bonded to the first metal pad . A concentration of silicon atoms in a bonded portion B of the first metal pad  and the second metal pad  is greater than a concentration of silicon atoms in a first portion P of the first metal pad  and is greater than a concentration of silicon atoms in a second portion P of the second metal pad 

Inventor

Shinya OKUDA

SEMICONDUCTOR MEMORY DEVICE (17929437)

Abstract

A substrate includes a first region and a second region around the first region. A layer stack is above the substrate in the first region in a first direction. A first conductor is on the substrate in the second region and extends in the first direction. A second conductor is on the first conductor and extends in a direction approaching the second region from the first region. A third conductor is on the second conductor and extends in the first direction, includes an upper surface reaching a height of an upper surface of the layer stack. The third conductor is positioned farther from the first region than the first conductor. The third conductor is not opposed to the first conductor in the first direction. A set of the first conductor, the second conductor, and the third conductor surrounds the first region.

Inventor

Hiroshi MATSUMOTO

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS (17890368)

Abstract

A semiconductor device includes a first device; and a second device bonded to the first device. The first device includes a plurality of first metal pads provided above a semiconductor substrate with an approximately circular shape; a first circuit coupled to at least one of the plurality of the first metal pads; and a first metal ring provided along an outer circumference of the semiconductor substrate to surround the first circuit. The second device includes a plurality of second metal pads joined to the plurality of the first metal pads, respectively; a second circuit coupled to at least one of the plurality of the second metal pads; and a second metal ring joined to the first metal ring.

Inventor

Yuji Setta

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE (17899909)

Abstract

A semiconductor device includes: a first electrode; a second electrode; a first oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode around the first oxide semiconductor layer; a second oxide semiconductor layer provided between the gate electrode and the first oxide semiconductor layer, and separated from the first electrode; and a gate insulating layer provided between the gate electrode and the second oxide semiconductor layer.

Inventor

Keiko SAKUMA

SEMICONDUCTOR INTEGRATED CIRCUIT, RECEIVER DEVICE, AND RECEPTION METHOD (17942743)

Abstract

According to one embodiment, a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. The adjustment circuit is configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value.

Inventor

Mai ARAKI

MEMORY SYSTEM AND CONTROL METHOD OF CONTROLLING NONVOLATILE MEMORY (17807038)

Abstract

A memory system includes a memory controller. The memory controller executes first calculation of obtaining a first degree to k-th degree error locator polynomials (1≤k<t) by using a syndrome, determines whether error locations can be calculated by the error locator polynomials up to the k-th degree, obtains an initial value of a parameter to be used for second calculation of obtaining error locator polynomials up to t-th degree when it is determined that the error locations cannot be calculated, executes the second calculation using the initial value, calculates the error locations by using an error locator polynomial determined to be able to calculate the error locations among the first degree to k-th degree error locator polynomials or by using error locator polynomials obtained in the second calculation, and corrects errors in the calculated error locations.

Inventor

Naoaki KOKUBUN

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PRODUCING THE SAME (17901077)

Abstract

A semiconductor memory device includes: a plate electrode; a plurality of memory capacitors arranged along a front surface of the plate electrode; and a plurality of memory transistors electrically connected to the plurality of memory capacitors. Each memory capacitor includes: a columnar first electrode electrically connected to the memory transistor; a dielectric layer provided on an outer periphery of the first electrode; a second electrode provided on an outer periphery of the dielectric layer and electrically connected to the plate electrode; and an insulating layer provided between the first electrode and the plate electrode and containing a material that is different from a material contained in the dielectric layer.

Inventor

Mutsumi OKAJIMA

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (17899876)

Abstract

A method for manufacturing a semiconductor device includes forming a hole through a first film; forming a semiconductor layer along a side surface of the hole; forming a second film overlaying a first region of the semiconductor layer; forming a third film along a side surface of a second region of the semiconductor layer that is above the first region; removing the second film to expose a side surface of the first region; forming a fourth film containing a plurality of first atoms and disposed along the side surface of the first region of the semiconductor layer; and diffusing the first atoms into the first region of the semiconductor layer.

Inventor

Naomi Yanai

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (17931569)

Abstract

In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a first substrate, forming a porous layer in a first portion of the first film and a non-porous layer in a second portion of the first film, forming a second film including a first device on the first film, forming a third film including a second device on a second substrate, and bonding the second film on the first substrate and the third film on the second substrate to be opposite to each other. Furthermore, the semiconductor device includes a first region and a second region. Moreover, the first device and the second device are located in the first region, the first portion is located among the first region and the second region, and the second portion is located in the second region.

Inventor

Hidekazu HAYASHI

NON-VOLATILE MEMORY DEVICE (18322306)

Abstract

According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

Inventor

Hiroki YAMASHITA

SEMICONDUCTOR MEMORY DEVICE (18138820)

Abstract

A method of controlling a memory device includes receiving a write instruction; starting a write operation to a first address in response to the write instruction; receiving a first read instruction of the first address; suspending the write operation; and applying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction. The method further includes resuming the write operation is after applying the read voltage; receiving a second read instruction after applying the read voltage; and outputting read data from a data register in response to the second read instruction during a period starting at resuming the write operation and ending at completion of the write operation.

Inventor

Koichiro YAMAGUCHI

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE (17806111)

Abstract

A semiconductor memory device of an embodiment includes: a semiconductor layer extending in a first direction; a gate electrode layer containing at least one element selected from a group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), and cobalt (Co); a first insulating layer provided between the semiconductor layer and the gate electrode layer; a charge storage layer provided between the first insulating layer and the gate electrode layer; a second insulating layer provided between the charge storage layer and the gate electrode layer; a third insulating layer provided between the second insulating layer and the gate electrode layer; and a metal oxide layer provided between the third insulating layer and the gate electrode layer and containing at least one first metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta).

Inventor

Saho OHSAWA

METHOD FOR MANUFACTURING OXIDE FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MEMORY DEVICE (17819039)

Abstract

A method for manufacturing an oxide film according to an embodiment includes forming a first film containing aluminum (Al) and nitrogen (N), and forming a second film containing aluminum (Al) and oxygen (O) by oxidizing the first film in an atmosphere containing heavy water (DO).

Inventor

Tsunehiro INO

SEMICONDUCTOR DEVICE (17899962)

Abstract

A semiconductor device includes a plurality of conductive layers stacked above one another in a first direction and including a first conductive layer, second conductive layers, and third conductive layers, a semiconductor film extending in the first direction through the conductive layers, an insulating film around the semiconductor film between the semiconductor film and the plurality of conductive layers. During a program operation performed on a first memory cell, a program voltage is applied to the first conductive layer while a first voltage is applied to the second conductive layers and a second voltage different from the first voltage is applied to the third conductive layers. The second conductive layers are each connected to gates of second memory cells programmed to store m bits, and the third conductive layers are each connected to gates of third memory cells programmed to store n bits, where n is different from m.

Inventor

Yuki INUZUKA

METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE (17901642)

Abstract

According to one embodiment, a method of manufacturing a semiconductor memory device includes: repeating multiple times of a process of etching away one pair of first and second insulating layers of a stacked body exposed from a second mask layer, among a plurality of first and second insulating layers, with retracting the second mask layer in a first direction toward a first side by slimming; removing the second mask layer undergone multiple times of the slimming; removing a first stopper layer exposed on the first side; and repeating multiple times of a process of etching away one pair of first and second insulating layers of the stacked body exposed from a first mask layer, among the plurality of first and second insulating layers, with retracting the first mask layer in the first direction by slimming.

Inventor

Kyosuke NANAMI

SEMICONDUCTOR STORAGE DEVICE (17883464)

Abstract

According to one embodiment, a semiconductor storage device includes a stacked body with conductive layers which are spaced apart one from another along a first direction. A pillar structure extends in the first direction through the conductive layers and has protruding parts, each of which protrudes outwardly from the pillar structure towards a conductive layer. The pillar structure includes a semiconductor layer, a tunnel insulating layers separately in each of the protruding parts between the semiconductor layer and the conductive layer. There is no tunnel insulating layer in the region between the adjacent protruding parts in the first direction. A charge storage layer is also separately in each protruding part between the tunnel insulating layer and the conductive layer.

Inventor

Takuya NISHIKAWA

SEMICONDUCTOR MEMORY DEVICE (17885739)

Abstract

A semiconductor memory device includes a semiconductor layer extending in a first direction, a conductive layer opposed to the semiconductor layer in a second direction intersecting with the first direction, an electric charge accumulating layer disposed between the semiconductor layer and the conductive layer, a first insulating layer disposed between the semiconductor layer and the electric charge accumulating layer, and a second insulating layer disposed between the conductive layer and the electric charge accumulating layer. The semiconductor layer includes at least one protrusion protruding in the second direction toward the electric charge accumulating layer. A position in the first direction of the protrusion is inside with respect to corner portions at both ends in the first direction of a surface opposed to the semiconductor layer in the electric charge accumulating layer.

Inventor

Tatsuki KOSHIDA

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE (17897065)

Abstract

A semiconductor device has a third region between first and second regions on a substrate surface. A gate insulating film which is above the third region. A gate electrode is above the gate insulating film and includes a metal-containing layer. A first conductor is above the gate electrode. A first voltage can be applied to the first conductor. A second conductor is above the first region. A second voltage can be applied to the second conductor. A third conductor is above the first region. A third voltage different from the first and second can be applied to the third conductor. A metal oxide film is provided between the first region and the third conductor. An upper surface of the metal oxide film includes a portion at a height from the substrate that is lower than a height of an upper surface of the metal-containing layer.

Inventor

Tadayoshi UECHI

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME (17941987)

Abstract

A semiconductor storage device includes a processing circuit provided on a substrate, a plurality of first electrodes connected to the processing circuit, and a plurality of second electrodes connected to the plurality of first electrodes. The semiconductor storage device also includes a memory cell array connected to the plurality of second electrodes. The memory cell array includes a block, and the block includes a string unit. Each string unit includes a plurality of memory cells, and a plurality of column-shaped parts penetrating through at least one stack body that is a stack of a plurality of electrode films between which an insulating film is interposed. The semiconductor storage device includes a slit insulating, for each string unit, a source line electrically connected to a portion of the plurality of memory cells and a source line electrically connected to another portion of the memory cells.

Inventor

Kenta YAMADA

MAGNETIC MEMORY DEVICE (17943151)

Abstract

According to one embodiment, a magnetic: memory device includes a stacked structure in which a magnetoresistance effect element and a switching element are stacked. The switching element is provided on a lower layer side of the magnetoresistance effect element, and when viewed in a stacking direction of the magnetoresistance effect element and the switching element, a pattern of the switching element is located inside a pattern of the magnetoresistance effect element.

Inventor

Kenichi YOSHINO

SEMICONDUCTOR MEMORY DEVICE (17901485)

Abstract

A semiconductor memory device includes a first wiring extending in a first direction; a second wiring extending in a second direction and spaced from the first wiring in a third direction; a stacked body disposed between the first and second wirings and including conductive layers and insulating layers alternately stacked on top of one another in the third direction; a columnar body extending through the stacked body and including: (a) an electrode disposed between the first wiring and the second wiring, (b) a memory layer disposed between the electrode and the conductive layers, and (c) a selection layer disposed between the electrode and the first wiring; and a diode disposed between the electrode and the second wiring.

Inventor

Katsuyoshi KOMATSU

MEMORY DEVICE (17901744)

Abstract

According to one embodiment, a memory device includes a first conductor layer and a second conductor layer spaced apart from each other in a first direction, a first semiconductor film spaced from the first conductor layer in a second direction intersecting the first direction, and a second semiconductor film spaced from the second conductor layer in the second direction. The first semiconductor film is between a first resistance change film and the first conductor layer in the second direction. The second semiconductor film is between a second resistance change film and the second conductor layer in the second direction. A first conductor film has a first end contacting the first semiconductor film and the first resistance change film and a second end contacting the second semiconductor film and the second resistance change film.

Inventor

Kensuke TAKAHASHI

MAGNETIC MEMORY DEVICE (17943723)

Abstract

According to one embodiment, a magnetic memory device includes a magnetoresistance effect element portion, a switching element portion provided on a lower layer side of the magnetoresistance effect element portion, a buffer insulating portion provided between the magnetoresistance effect element portion and the switching element portion, and a conductive portion surrounding a side surface of the buffer insulating portion and electrically connecting the magnetoresistance effect element portion and the switching element portion to each other.

Inventor

Yuichi ITO

SWITCHING ELEMENT AND MEMORY DEVICE (17943763)

Abstract

According to one embodiment, a switching element includes a first electrode, a second electrode, and a switching material layer provided between the first electrode and the second electrode. The switching material layer contains silicon (Si), oxygen (O), arsenic (As), and a predetermined element selected from lead (Pb), silver (Ag), indium (In), tin (Sn), copper (Cu), zinc (Zn), gallium (Ga), germanium (Ge), selenium (Se), antimony (Sb), tellurium (Te), gold (Au) and bismuth (Bi).

Inventor

Taichi IGARASHI

SEMICONDUCTOR STORAGE DEVICE (17901690)

Abstract

According to one embodiment, a semiconductor storage device includes a first electrode and a second electrode spaced in a first direction and a phase change layer provided between the first electrode and the second electrode. The phase change layer comprises at least one of germanium (Ge), antimony (Sb), and tellurium (Te). The phase change layer is configured to be able to transition to a first state in which a volume ratio of an amorphous phase to a crystalline phase is a first ratio, a second state in which the volume ratio is a second ratio larger than the first ratio, and a third state in which the volume ratio is a third ratio larger than the second ratio.

Inventor

Hiroyuki ODE