International business machines corporation (20240121933). STACKED-FET SRAM CELL WITH BOTTOM pFET simplified abstract
Contents
- 1 STACKED-FET SRAM CELL WITH BOTTOM pFET
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 STACKED-FET SRAM CELL WITH BOTTOM pFET - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
STACKED-FET SRAM CELL WITH BOTTOM pFET
Organization Name
international business machines corporation
Inventor(s)
Gen Tsutsui of Glenmont NY (US)
Shogo Mochizuki of Mechanicville NY (US)
Ruilong Xie of Niskayuna NY (US)
STACKED-FET SRAM CELL WITH BOTTOM pFET - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240121933 titled 'STACKED-FET SRAM CELL WITH BOTTOM pFET
Simplified Explanation
The semiconductor structure described in the abstract includes a bottom field effect transistor (FET) with bottom source/drain (S/D) epi regions, a top FET with top S/D epi regions, a bonding dielectric layer between the two FETs, and a node contact extending from a bottom S/D epi region of the bottom FET through the bonding dielectric layer into the top FET. The bottom FET has an inverter gate, while the top FET connects to back-end-of-line (BEOL) components and the bottom FET connects to a backside power delivery network (BSPDN).
- Bottom FET with bottom S/D epi regions
- Top FET with top S/D epi regions
- Bonding dielectric layer between bottom and top FETs
- Node contact extending from bottom FET to top FET
- Top FET connects to BEOL components
- Bottom FET connects to BSPDN
Potential Applications
This semiconductor structure could be used in various electronic devices such as smartphones, tablets, laptops, and other portable electronics where efficient power delivery and connectivity are essential.
Problems Solved
This innovation solves the problem of efficiently connecting different components within a semiconductor structure while maintaining high performance and reliability.
Benefits
The benefits of this technology include improved power delivery, enhanced connectivity, and overall better performance of electronic devices.
Potential Commercial Applications
This technology could be applied in the semiconductor industry for manufacturing advanced integrated circuits and electronic devices.
Possible Prior Art
One possible prior art could be the use of bonding dielectric layers in semiconductor structures to improve connectivity and performance.
Unanswered Questions
How does this semiconductor structure compare to existing technologies in terms of power efficiency and performance?
This article does not provide a direct comparison with existing technologies in terms of power efficiency and performance.
What are the specific materials and manufacturing processes used to create this semiconductor structure?
The article does not delve into the specific materials and manufacturing processes used to create this semiconductor structure.
Original Abstract Submitted
a semiconductor structure is presented including a bottom field effect transistor (fet) including a plurality of bottom source/drain (s/d) epi regions, a top fet including a plurality of top s/d epi regions, a bonding dielectric layer disposed directly between the bottom fet and the top fet, and a node contact advantageously extending from a bottom s/d epi region of the plurality of bottom s/d epi regions of the bottom fet through the bonding dielectric layer and into the top fet. the bottom fet includes an inverter gate. the top fet electrically connects to back-end-of-line (beol) components and the bottom fet electrically connects to a backside power delivery network (bspdn).
