International business machines corporation (20240113162). MONOLITHIC STACKED FIELD EFFECT TRANSISTOR (SFET) WITH DUAL MIDDLE DIELECTRIC ISOLATION (MDI) SEPARATION simplified abstract

MONOLITHIC STACKED FIELD EFFECT TRANSISTOR (SFET) WITH DUAL MIDDLE DIELECTRIC ISOLATION (MDI) SEPARATION

Organization Name

international business machines corporation

Inventor(s)

Jingyun Zhang of Albany NY (US)

Ruilong Xie of Niskayuna NY (US)

Julien Frougier of Albany NY (US)

Ruqiang Bao of Niskayuna NY (US)

Prabudhya Roy Chowdhury of Albany NY (US)

MONOLITHIC STACKED FIELD EFFECT TRANSISTOR (SFET) WITH DUAL MIDDLE DIELECTRIC ISOLATION (MDI) SEPARATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240113162 titled 'MONOLITHIC STACKED FIELD EFFECT TRANSISTOR (SFET) WITH DUAL MIDDLE DIELECTRIC ISOLATION (MDI) SEPARATION

Simplified Explanation

The abstract of the patent application describes a method for processing monolithic stacked field effect transistors with dual middle dielectric isolation separation. This involves forming two nanosheets stacked vertically, each with a gate around its channel region and a middle dielectric isolation structure between them.

• Formation of dual middle dielectric isolation separation in monolithic stacked field effect transistors
• Stacking of two nanosheets with gates around their channel regions
• Creation of a middle dielectric isolation structure between the nanosheets
• Structure includes two middle dielectric isolation layers stacked vertically
• Gate extends between the middle dielectric isolation layers

Potential Applications

The technology described in the patent application could have potential applications in:

• Semiconductor manufacturing
• Integrated circuits
• Nanoelectronics

Problems Solved

The technology addresses the following problems:

• Improving performance and efficiency of field effect transistors
• Enhancing isolation between stacked nanosheets
• Increasing density of transistors in a monolithic structure

Benefits

The technology offers the following benefits:

• Higher transistor density
• Improved transistor performance
• Enhanced isolation between transistors
• Potential for smaller and more efficient electronic devices

Potential Commercial Applications

The technology could find commercial applications in:

• Semiconductor industry
• Electronics manufacturing
• Mobile devices and computers

Possible Prior Art

One possible prior art in this field is the use of traditional dielectric isolation techniques in semiconductor manufacturing processes.

Unanswered Questions

How does this technology compare to existing methods for isolating stacked transistors?

The article does not provide a direct comparison between this technology and other methods for isolating stacked transistors.

What are the specific performance improvements achieved with this dual middle dielectric isolation structure?

The article does not detail the specific performance improvements achieved with the dual middle dielectric isolation structure.

Original Abstract Submitted

embodiments of the present invention are directed to monolithic stacked field effect transistor (sfet) processing methods and resulting structures having dual middle dielectric isolation (mdi) separation. in a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. a gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. the middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. a portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.