International business machines corporation (20240105244). STACKED FET WITH THREE-TERMINAL SOT MRAM simplified abstract

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STACKED FET WITH THREE-TERMINAL SOT MRAM

Organization Name

international business machines corporation

Inventor(s)

Pouya Hashemi of Purchase NY (US)

Ruilong Xie of Niskayuna NY (US)

STACKED FET WITH THREE-TERMINAL SOT MRAM - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240105244 titled 'STACKED FET WITH THREE-TERMINAL SOT MRAM

Simplified Explanation

The abstract describes a three-terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device with specific components and configurations.

  • The device includes a first type field effect transistor (FET) that drives an SOT line and has a write gate in contact with a write wordline (WWL).
  • It also features a second type FET in contact with a magnetic tunnel junction (MTJ) and a read gate in contact with a read wordline (RWL).
  • The first type FET is positioned above the second type FET, providing a density of three contacted poly pitch (CPP) per two cells.

Potential Applications

This technology could be applied in data storage devices, computer memory systems, and other electronic devices requiring non-volatile memory.

Problems Solved

This innovation addresses the need for high-density, low-power, and fast-access memory solutions in modern electronics.

Benefits

The three-terminal SOT MRAM device offers improved performance, increased density, and lower power consumption compared to traditional memory technologies.

Potential Commercial Applications

Potential commercial applications include smartphones, tablets, laptops, servers, and other electronic devices that require reliable and efficient memory storage solutions.

Possible Prior Art

Prior art in the field of MRAM devices may include research on different types of MRAM structures, materials, and configurations to improve memory performance and efficiency.

Unanswered Questions

How does the performance of this three-terminal SOT MRAM device compare to other types of MRAM technologies in terms of speed and energy efficiency?

Further testing and benchmarking against existing MRAM technologies would be needed to determine the device's performance metrics accurately.

Are there any limitations or drawbacks to implementing this three-terminal SOT MRAM device in practical electronic systems?

Exploring potential challenges, such as manufacturing complexity or compatibility issues with existing hardware, could provide a more comprehensive understanding of the technology's feasibility.


Original Abstract Submitted

embodiments are disclosed for a three-terminal spin-orbit-torque (sot) magnetoresistive random access memory (mram) device. the three-terminal sot mram device includes a first type field effect transistor (fet) that drives an sot line. additionally, the first type fet includes a write gate in electrical contact with a write wordline (wwl). further, the device also includes a second type fet in electrical contact with a magnetic tunnel junction (mtj). also, the second type fet comprises a read gate in electrical contact with a read wordline (rwl). additionally, the first type fet is disposed above the second type fet. further, the three-terminal sot mram device provides a density of three contacted poly pitch (cpp) per two cells.